54ACT109

Supply Voltage (V_CC).........-0.5V to +7.0V
DC Input Diode Current (I_IK)
V_I = -0.5V ...................-20 mA
V_I = V_CC + 0.5V................ +20 mA
DC Input Voltage (V_I) ..... .-0.5V to V_CC + 0.5V
DC Output Diode Current (I_OK)
V_O = -0.5V................ ... 20 mA
V_O = V_CC + 0.5V................ +20 mA
DC Output Voltage (V_O) ..... .-0.5V to V_CC + 0.5V
DC Output Source
or Sink Current (I_O) ............. .±50 mA
DC V_CC or Ground Current
per Output Pin (ICC or IGND) ..........±50 mA
Storage Temperature (T_STG) .... .-65°C to +150°C
Junction Temperature (T_J)
CDIP........................ 175°C
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply,temperature, and output/input loading variables. National does not recommend operation of FACT® circuits outside databook specifications.

The 54ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to 'AC/'ACT74 data sheet) by connecting the J and K inputs together.

54ACT109 Asynchronous Inputs:
LOW input to S_D (Set) sets Q to HIGH level
LOW input to C_D (Clear) sets Q to LOW level
Clear and Set are independent of clock

The 54ACT109 consists of two high-speed completely independent transition clocked JK# flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK# design allows operation as a D flip-flop (refer to 'AC/'ACT74 data sheet) by connecting the J and K# inputs together.

54ACT109 Asynchronous Inputs:

LOW input to S#_D (Set) sets Q to HIGH level

LOW input to C#_D (Clear) sets Q to LOW level

Clear and Set are independent of clock

Simultaneous LOW on C#_D and S#_D makes both Q and Q#

HIGH

Application Notes