54AC273

Features:

` Ideal buffer for microprocessor or memory
` Eight edge-triggered D flip-flops
` Buffered common clock
` Buffered, asynchronous master reset
` See '377 for clock enable version
` See '373 for transparent latch version
` See '374 for TRI-STATE® version
` Outputs source/sink 24 mA
` 'ACT has TTL-compatible inputs
` Standard Military Drawing (SMD)
-'AC273: 5962-87756




Pinout






Specifications

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Supply Voltage (V_CC) −0.5V to +7.0V
DC Input Diode Current (I_IK)
V_I = −0.5V −20 mA
V_I = V_CC + 0.5V +20 mA
DC Input Voltage (V_I) −0.5V to V_CC + 0.5V
DC Output Diode Current (I_OK)
V_O = −0.5V −20 mA
V_O = V_CC + 0.5V+20 mA
DC Output Voltage (V_O) −0.5V to to V_CC + 0.5V
DC Output Source
or Sink Current (I_O) ±50 mA
DC VCC or Ground Current
per Output Pin (I_CC or IGND)±50 mA
Storage Temperature (T_STG) −65°C to +150°C
Junction Temperature (T_J)
CDIP 175°C

Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT™ circuits outside databook specifications.

Temperature Min	-55 deg C
Temperature Max	125 deg C
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Description

The 54AC273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously.

The register 54AC273 is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output.

All outputs of 54AC273 will be forced LOW independently of Clock or Data inputs by a LOW voltage level on theMR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.

The 54AC273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR#) input load and reset (clear) all flip-flops simultaneously.

The register 54AC273 is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output.

All outputs of 54AC273 will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR# input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.

Application Notes

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Title	Size in Kbytes	Date
AN-925: Radiation Design Test Data for Advanced CMOS Product	194 Kbytes	5-Aug-95	Download

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