Features: `ICC reduced by 50%
`Synchronous counting and loading
`Built-In lookahead carry capability
`Presettable for programmable operation
`Outputs source/sink 24 mA
` 'ACT has TTL-compatible inputs
`Standard Microcircuit Drawing (SMD) 5962-91603Pinout
SpecificationsIf Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Supply Voltage (VCC)..... -0.5V to +7.0V
DC Input Diode Current (IIK)
VI = -0.5V ...............-20 mA
VI = VCC + 0.5V ............+20 mA
DC Input Voltage (VI) ...-0.5V to VCC + 0.5V
DC Output Diode Current (IOK)
VO = -0.5V.............. .-20 mA
VO = VCC + 0.5V............ +20 mA
DC Output Voltage (VO).-0.5V to to VCC + 0.5V
DC Output Source
or Sink Current (IO) ..........±50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND) ......±50 mA
Storage Temperature (TSTG) .−65C to +150
Junction Temperature (TJ)
CDIP ....................175
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply,temperature, and output/input loading variables. National does not recommend operation of FACT® circuits outside databook specifications.
| Temperature Min |
-55 deg C |
| Temperature Max |
125 deg C |
| View Using Catalog |
DescriptionThe 54AC169 is fully synchronous 4-stage up/down counter. The 54AC169 is a modulo-16 binary counter. It features a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH transition of the Clock.
The 54AC169 is fully synchronous 4-stage up/down counter. The 54AC169 is a modulo-16 binary counter. It features a preset capability for programmable operation, carry lookahead for easy cascading and a U/D# input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH transition of the Clock.
More Application Notes
| Title |
Size in Kbytes |
Date |
|
| AN-932: SEU and Latch Up Tolerant Advanced CMOS Technology |
186 Kbytes |
5-Jan-96 |
Download |
| AN-925: Radiation Design Test Data for Advanced CMOS Product |
194 Kbytes |
5-Aug-95 |
Download |
| AN-927: Total Dose Testing of Advanced CMOS Logic at Low Voltage |
109 Kbytes |
5-Jan-96 |
Download |
| AN-989: AN-989 Single Event Upset and Latchup Considerations for CMOS Devices Operated at 3.3 V |
91 Kbytes |
6-Oct-99 |
Download |
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54AC169 Data Sheet
