54AC16373

Features:

Members of the Texas Instruments Widebus(TM) Family
3-State True Outputs
Full Parallel Access for Loading
Flow-Through Architecture Optimizes PCB Layout
Distributed V_CC  and GND Pin Configuration Minimizes High-Speed Switching Noise
EPIC(TM) (Enhanced-Performance Implanted CMOS) 1-m m Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings


Pinout




Specifications

Supply voltage range, V_CC   . . . . . . . . . . . . . . . .  . . . . . . . . . . .0.5 V to 7 V
Input voltage range, V_I  (see Note 1)  . . . . . . . . . . . . 0.5 V to V_CC  + 0.5 V
Output voltage range, V_O  (see Note 1)  . . . . . . . . .  .0.5 V to V_CC  + 0.5 V
Input clamp current, I_IK  (V_I  < 0 or V_I > V_CC )  . . . . . . . . . . .. . . . . . .  20 mA
Output clamp current, I_OK (V_O   < 0  or V_O  > V_CC )  . . . . . .. . . . . .  ± 50 mA
Continuous output current, I_O  (V_O  = 0 to V_CC )  . . . . . . . . . . . . . .  ±50 mA
Continuous current through V_CC  or GND  . . . . . . . . . . .. . . . . . . . . ±400 mA
Maximum power dissipation at T_A   = 55° C
(in still air) (see Note 2): DL package  . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 W
Storage temperature range, T  . . . . . . . . . . . . . . . . . . . . . 65° C to 150⁰C


Description

The 54AC16373 are 16-bit transparent D-type 2Q5 19 30 2D5 latches with 3-state outputs designed specifically 2Q6 20 29 2D6 for driving highly capacitive or relatively GND 21 28 GND low-impedance loads. They are particularly 2Q7 22 27 2D7 suitable for implementing buffer registers, I/O 2Q8 23 26 2D8 ports, bidirectional bus drivers, and working 2OE 24 25 2LE registers. The 54AC16373 can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE of54AC16373 is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (OE) input of 54AC16373 can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the 54AC16373 latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The 54AC16373 is packaged in TI's shrink small-outline package (DL), which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.

The 54AC16373 is characterized for operation over the full military temperature range of 55°C to 125°C. The 74AC16373 is characterized for operation from 40°C to 85°C.