Features: • Eight D-Type Flip-Flops in a Single Package
• 3-State Bus Driving Inverting Outputs
• Full Parallel Access for Loading
• Inputs Are TTL-Voltage Compatible
• Flow-Through Architecture to Optimize PCB Layout
• Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise
• EPIC™ (Enhanced-Performance Implanted CMOS) 1-m Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic Small- Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPsPinout
SpecificationsSupply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Storage temperature range . . . . . . . . . . . . . . . . . . .. . . . . . . .. 65°C to 150°C
‡ Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
DescriptionThese eight flip-flops 54AC11534 feature 3-state outputs designed for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight flip-flops of the 54AC11534 are edgetriggered, D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the complement of the logic levels at the D inputs. The 54AC11534 is functionally equivalent to the 4AC11374 except for having inverted outputs.
An output-control input (OC) of 54AC11534 is used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance third state and increased drive provide the capability to drive the bus lines in a bus-organized system without need for interface or pull-up components. The output control (OC) of 54AC11534 does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The 54AC11534 is characterized for operation over the full military temperature range of 55°C to 125°C. The 74AC11534 is characterized for operation from 40°C to 85°C.
54AC11534 Data Sheet
