Features: • Permits Multiplexing From N Lines to One Line• Performs Parallel-to-Serial Conversion• Flow-Through Architecture Optimizes PCB Layout• Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise• EPIC (Enhanced-Performance Implanted CMOS) 1-...
54AC11253: Features: • Permits Multiplexing From N Lines to One Line• Performs Parallel-to-Serial Conversion• Flow-Through Architecture Optimizes PCB Layout• Center-Pin VCC and GND Conf...
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Each of these data selectors/multiplexers 54AC11253 contains inverters and drivers to supply full binary decoding data selection to the AND-OR gates. Separate output control inputs are provided for each of the two four-line sections.
The three-state outputs of 54AC11253 can interface with and drive data lines of bus-organized systems. With all but one of the common outputs disabled (at a high-impedance state), the low-impedance of the single enabled output will drive the bus line to a high or low logic level. Each output has its own strobe (G). The output of 54AC11253 is disabled when its strobe is high.
The 54AC11253 is characterized for operation over the full military temperature range of 55 to 125. The 74AC11253 is characterized for operation from 40 to 85.