Features: • Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems
• Noninverting Version of 4AC11138
• Incorporates 3 Enable Inputs to Simplify Cascading and/or Data Reception
• Flow-Through Architecture Optimizes PCB Layout
• Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
• EPIC™ (Enhanced-Performance Implanted CMOS) 1-m Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPsPinout
SpecificationsSupply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Storage temperature range . . . . . . . . . . . . . . . . . . .. . . . . . . .. 65°C to 150°C
‡ Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
DescriptionThe 54AC11238 circuit is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder 54AC11238 can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the 54AC11238 decoder is negligible.
The conditions at the binary select inputs and the three enable inputs select one of eight input lines. Two active-low and one active-high enable inputs of 54AC11238 reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input of 54AC11238 can be used as a data input for demultiplexing applications.
The 54AC11238 is characterized for operation over the full military temperature range of 55°C to 125°C. The 74AC11238 is characterized for operation from 40°C to 85°C.
54AC11238 Data Sheet
