Features: • Flow-Through Architecture Optimizes PCB Layout• Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise• EPICE (Enhanced-Performance Implanted CMOS) 1-mm Process• 500-mA Typical Latch-Up Immunity at 125°C• ESD Protection Exceeds 2000 V, M...
54AC11109: Features: • Flow-Through Architecture Optimizes PCB Layout• Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise• EPICE (Enhanced-Performance Implanted CMOS) 1...
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Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Storage temperature range . . . . . . . . . . . . . . . . . . .. . . . . . . .. 65°C to 150°C
‡ Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
These 54AC11109 contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering of 54AC11109 occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops 54AC11109 can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops by tying the J and K inputs together.
The 54AC11109 is characterized for operation over the full military temperature range of 55°C to 125°C. The 74AC11109 is characterized for operation from 40°C to 85°C.