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54ABT273

Features: *Eight edge-triggered D flip-flops* Buffered common clock* Buffered, asynchronous Master Reset* See 'ABT377 for clock enable version* See 'ABT373 for transparent latch version* See 'ABT374 for TRI-STATE® version* Output sink capability of 48 mA, source capability of 24 mA* Guaranteed...

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SeekIC No. : 004233021 Detail

54ABT273: Features: *Eight edge-triggered D flip-flops* Buffered common clock* Buffered, asynchronous Master Reset* See 'ABT377 for clock enable version* See 'ABT373 for transparent latch version* See 'ABT374...

54ABT273 Data Sheet

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Part Number:
54ABT273
Supply Ability:
5000

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  • 1~5000
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  • 15 Days
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Product Details

Description



Features:

* Eight edge-triggered D flip-flops
* Buffered common clock
* Buffered, asynchronous Master Reset
* See 'ABT377 for clock enable version
* See 'ABT373 for transparent latch version
* See 'ABT374 for TRI-STATE® version
* Output sink capability of 48 mA, source capability of
   24 mA
* Guaranteed latchup protection
* High impedance glitch free bus loading during entire
   power up and power down cycle
* Non-destructive hot insertion capability
* Disable time less than enable time to avoid bus
   contention
* Standard Microcircuit Drawing (SMD) 5962-9321701


Pinout

Connection Diagram


Specifications

Storage Temperature .................................................................................−65 to +150
Ambient Temperature under Bias ...............................................................−55 to +125
Junction Temperature under Bias
   Ceramic ...................................................................................................−55 to +175
VCC Pin Potential to
   Ground Pin ................................................................................................−0.5V to +7.0V
Input Voltage (Note 2) ................................................................................−0.5V to +7.0V
Input Current (Note 2) ..........................................................................−30 mA to +5.0 mA
Voltage Applied to Any Output
   in the Disabled or
   Power-Off State .....................................................................................−0.5V to +4.75V
   in the HIGH State .......................................................................................−0.5V to VCC
Current Applied to Output
   in LOW State (Max) ...................................................................twice the rated IOL (mA)
DC Latchup Source Current ..................................................................................−500 mA
   (Across Comm Operating Range)
Over Voltage Latchup .......................................................................................VCC + 4.5V


Description

The 54ABT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.
The register 54ABT273 is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output.
All outputs of 54ABT273 will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The 54ABT273 is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.




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