542MLF

Output Logic Level :
Packaging :
Maximum Operating Temperature : + 70 C
Supply Voltage - Min : 3 V
Package / Case : SOIC-8
Supply Voltage - Max : 5.5 V


Specifications

No. of Inputs 1 Temperature C Input Type CMOS No. of Outputs 2 Output Type CMOS Voltage 3.3 V Package SOIC 8 Speed NA Max. Input Frequency 156 MHz,156 Output to Output Skew 500 ps Dividers/Multipliers /2,/4,/8,/12,/16 Core Supply Voltage (VDD) 3.3 V to 5 V,3.3V - 5V Output Supply Voltage (VDDO) 3.3 V to 5 V,3.3V - 5V Output Style SE Min. Output Frequency 0 Min. Input Frequency 0 Input Style SE Max. Output Frequency 156 Temp. Grade C,I Divide Value /2,/4,/6,/8,/12,/16


Description

CLOCK DIVIDER
The 542MLF is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz.

Using proprietary Phase-Locked Loop (PLL) techniques, the 542MLF produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on the chip, one being a low-skew divide by two of the other.

542MLF features:

8-pin SOIC package

Low-cost clock divider

Low-skew (500 ps) outputs. One is /2 of the other

Easy to use with other generators and buffers

Input clock frequency up to 156 MHz

Output clock duty cycle of 45/55

Power-down turns off chip

Output Enable

Full CMOS clock swings with 25 mA drive capability at TTL levels

Advanced, low power CMOS process

Operating voltage of 3.3 or 5 V