50S116T

50S116T is a high-speed synchronous dynamic random access memory (SDRAM), organized as 512K words ¥2 banks ¥16 bits. Using pipelined architecture 50S116T delivers a data bandwidth of up to 400M bytes per second (-5). For different applications the 50S116T is sorted  into  the following speed grades:  -5,  -6,  -7. The  -5 parts can run up to 200MHz/CL3.The -6 parts can run up to 166 MHz/CL3. The -7 parts can run up to 143 MHz/CL3. For handheld device application.

Accesses to the SDRAM 50S116T are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE  command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read of 50S116T is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.

By having a programmable Mode Register, the system can change burst length, latency cycle,interleave or sequential burst to maximize its performance. 50S116T is ideal for main memory in high performance applications.