503MLF

Specifications

Input Frequency 2 MHz to 50 MHz No. of Inputs 1 Temperature C Output Frequency 4 MHz to 160 MHz Input Type Clock,Crystal No. of Outputs 1 Output Type CMOS Voltage 3.3 V Package SOIC 8 Speed NA Core Supply Voltage (VDD) 3.3 V to 5 V Output Supply Voltage (VDDO) 3.3 V to 5 V Peak-to-Peak Period Jitter ± 100 ps Pk-to-Pk


Description

LOCO PLL CLOCK MULTIPLIER
The 503MLF is the most cost effective way to generate a high quality, high frequency clock output from a low frequency crystal or clock input, and is designed to replace crystals and crystal oscillators in most electronic systems. Using Phase-Locked-Loop (PLL) techniques, the 503MLF uses a standard fundamental mode, inexpensive crystal to produce output clocks up to 160 MHz. Stored in the chip|s ROM 503MLF is the ability to generate 9 different multiplication factors, allowing one chip to be used in two or three different applications.

503MLF features:

Packaged as 8 pin SOIC or die

Lowest cost PLL clock family

Generates 16.9344 MHz for stereo codecs from the 14.31818 MHz motherboard clock

Can be cost effective in replacing a single surface-mount crystal

Can be driven by other 5xx series

Input crystal frequency of 5 - 27 MHz

Input clock frequency of 2 - 50 MHz

Output clock frequencies up to 160 MHz

Low jitter - 50 ps one sigma

Duty cycle of 45/55 up to 160 MHz

Operating voltages of 3.0 to 5.5 V

Full CMOS level outputs with 25mA drive capability at TTL levels

Advanced, low power CMOS process