501AMILF

Specifications

Input Frequency 8 MHz to 50 MHz No. of Inputs 1 Temperature I Output Frequency 60 MHz to 200 MHz Input Type Clock,Crystal No. of Outputs 1 Output Type LVCMOS Voltage 3.3 V Package SOIC 8 Speed NA Core Supply Voltage (VDD) 3.3 V Output Supply Voltage (VDDO) 3.3 V Peak-to-Peak Period Jitter ± 70 ps Pk-to-Pk Banks 10 Chipset JR


Description

LOCO PLL CLOCK MULTIPLIER
The 501AMILF is the most cost effective way to generate a high-quality, high-frequency clock output from a lower frequency crystal or clock input, and is designed to replace crystal oscillators in most electronic systems. Using Phase-Locked Loop (PLL) techniques, the 501AMILF uses a standard fundamental mode, inexpensive crystal to produce output clocks up to 200 MHz.

Stored in the chip's ROM 501AMILF is the ability to generate nine different multiplication factors, allowing one chip to output many common frequencies.

The 501AMILF also has an Output Enable pin that tri-states the clock output when the OE pin is taken low.

This 501AMILF is intended for clock generation. It has low output jitter (variation in the output period), but input to output skew and jitter are not defined or guaranteed. For applications which require defined input to output skew, use the ICS570B.

501AMILF features:

Packaged as 8 pin-SOIC or die

IDT's lowest cost PLL clock

Zero ppm multiplication error

Input crystal frequency of up to 27 MHz

Input clock frequency of up to 50 MHz

Output clock frequencies up to 200 MHz

Extremely low jitter - 25 ps (one sigma)

Compatible with all popular CPUs

Duty cycle of 45/55 up to 200 MHz

Nine selectable frequencies

Operating voltages of 3.3 V

Tri-state output for board level testing

25 mA drive capability at TTL levels

Ideal for oscillator replacement

Optimized for output frequencies of up to 200 MHz (166 MHz maximum for industrial temperature version)

Industrial temperature version available

Advanced, low-power CMOS process