4510B

The 4510B is a kind of edge-triggered synchronous up/down BCD counter with a clock input (CP), an active HIGH up/down count control input (up/dn), an active LOW count enable input (CE), an asynchronous active HIGH parallel load input (PL), four parallel inputs (P0-P3), four parallel outputs (Q0-Q3), an active LOW terminal count output (TC) and an overriding asynchronous master reset input (MR).

There are some features about 4510B as follows: (1)up/down count control; (2)single clock input (LH edge triggered); (3)asynchronous parallel load input; (4)asynchronous master reset; (5)easily cascadable.

The last one is about the AC characteristics and set-up requirements about 4510B: VSS=0 V, TA=25, CL=50 pF, RL=200 k, input transition times20 ns: (1)twCP at VDD=5 V, CP minimum pulse width: 125 ns min and 50 ns typ; (2)twCP at VDD=10 V, CP minimum pulse width: 60 ns min and 21 ns typ; (3)twCP at VDD=15 V, CP minimum pulse width: 48 ns min and 14 ns typ ; (4)twMR at VDD=5 V, MR minimum pulse width: 150 ns min and 60 ns typ; (5)twMR at VDD=10 V, MR minimum pulse width: 60 ns min and 30 ns typ; (6)twMR at VDD=15 V, MR minimum pulse width: 48 ns min and 20 ns typ.