450KX

The 450KX has the following features including Host-to-PCI Bridge (PB):Combines Both the Control and Data Path in a Single Chip,internal Bridge Arbifer For Two PBs in a system(450GX),Synchronous PCI Interface,32-bit Address/Data PCI Bus (64-bit Dual Cycle Address Support);Parity Protection on All PCI Bus Signals;Four Deep Inbound Request Queue;Data Collection/Write Assembly of Line Bursts,Support for 3.3V&5V PCI Devices,Available in BGA 304 Pin QFP or 352 pin.

The Intel 450KX PClsets provide a high-performance system solution for Pro processor-based Pentium PCI systems by combining high integration,high performance technology with a scalable architecture that is capable of high throughput for up to four Pentium Pro processors. Scalability of 450KX provides a wide range of system solutions from cost-effective uniprocessor systems to high-end multiprocessor systems without sacrificing performance. For systems requiring extensive I/O(e.g.,file servers), a second PB of 450KX can be easily added providing two high-performance PCI bus structures.The flexibility of the memory controller permits easy expansion from a simple non-interleaved organization to a 2-way or 4-way interleaved organization to increase performance. Extended error checking and logging, ECC, and the ability to build in redundancy (e.g, multiple processors and dual PCI bridges) provides a comprehensive solution for systems requiring high reliability.The PClset may contain design defects or errors known as errata. Current of 450KX characterized errata are available upen request.

The PB 450KX is a single-chip host-to-PCI Bridge. A rich set of CPU-to-PCI and PCI-to-CPU bus transaction translations optimize bus bandwidth and improve system pertormance. All ISA and EISA regions are supported. Three programmable memory gaps can be created-a PCI Frame Buffer Region with specialized frame buffer attributes and two general-purpose memory gaps (called the Memory Gap Region and the High Memory Gap Region).The MC of 450KX is PC compatible. All ISA and EISA regions are decoded and shadowed based on programmable configurations.Regions above 1 Mbyte with size 1 Mbyte or larger that are not mapped to memory may be reclaimed by setting the appropriate configuration in the MC. Three programmable memory gaps of 450KX can be created and are called the Low Memory Gap Region, the Memory Gap Region and the High Memory Gap Region.