Features: • Complies with Bellcore and ITU-T specifications• Jitter generation better than ITU-T requirements• On-chip high-frequency PLL for clock generation• Supports 155.52 Mbps (OC-3) and 622.08 Mbps (OC-12)• Selectable reference frequencies of 19.44, 38.88, 51.84...
43584: Features: • Complies with Bellcore and ITU-T specifications• Jitter generation better than ITU-T requirements• On-chip high-frequency PLL for clock generation• Supports 155.5...
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Symbol |
PARAMETER |
TYP
|
Unit |
CONDITIONS |
PIN |
VDD =2.7V, CTL=0V/2.7V |
dBm |
37 | |
VDD |
Supply Voltage |
VDD terminal |
V |
7.5 |
VCTL |
Control Voltage |
CTL terminal
|
V |
7.5 |
PD |
Power Dissipation |
mW |
250 | |
IOUT |
Operating Temp. |
°C |
-40~+85 | |
Tstg |
Storage Temp. |
°C |
-55~+150 |
The S3028 SONET/SDH transceiver chip is a fully integrated serialization/deserialization SONET OC-12 (622.08 Mbit/s) and OC-3 (155.52 Mbit/s) interface device. The S3028 performs all necessary serial-to-parallel and parallel-to-serial functions in conformance with SONET/SDH transmission standards.
The S3028 is suitable for SONET-based ATM applications and can be used in conjunction with AMCC's S3026 Clock Recovery Unit (CRU). Figure 1 shows a typical network application. On-chip clock synthesis is performed by the highfrequency phase-locked loop on the S3028 transceiver chip allowing the use of a slower external transmit clock reference.
The S3028 also performs SONET/SDH frame detection. The chip can be used with a 19.44, 38.88, 51.84 or 77.76 MHz reference clock, in support of existing system clocking schemes.
The low jitter PECL interface guarantees compliance with the bit-error rate requirements of the Bellcore and ITU-T standards.
The S3028 is packaged in a 64 PQFP, offering designers a small package outline. Since the S3028 jitter generation is better than the ITU-T requirements over all reference frequencies, the designer can meet the overall system requirement including the optical interface devices (refer to Table 9 for jitter generation specifications).