Features: Complementary outputs Direct overriding (data) inputsGated clock inputsParallel-to-serial data conversionTypical frequency 35 MHzTypical power dissipation 105 mWSpecificationsSupply Voltage .................................................................7VInput Voltage ....................
42271: Features: Complementary outputs Direct overriding (data) inputsGated clock inputsParallel-to-serial data conversionTypical frequency 35 MHzTypical power dissipation 105 mWSpecificationsSupply Voltag...
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Supply Voltage .................................................................7V
Input Voltage ...................................................................7V
Operating Free Air Temperature Range .......0°C to +70°C
Storage Temperature ............................−65°C to +150°C
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation.
This 42271 is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked. Parallel-in access is made available by eight individual direct data inputs, which are enabled by a low level at the shift/load input. These 42271 registers also feature gated clock inputs and complementary outputs from the eighth bit.
Clocking is accomplished through a 2-input NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs HIGH inhibits clocking, and holding either clock input LOW with the load input HIGH enables the other clock input. The clock-inhibit input of 42271 should be changed to the high level only while the clock input is HIGH. Parallel loading is inhibited as long as the load input is HIGH. Data at the parallel inputs are loaded directly into the 42271 register on a HIGH-to-LOW transition of the shift/load input, regardless of the logic levels on the clock, clock inhibit, or serial inputs.