Features: Organization 512K-Byte Main Array 24K-Byte Protected Overlay-Block User-Defined x16 or x32 Data Bus Read Transfer Data Rates Up to 100 MBytes/s at Bus Frequencies Up to 40 MHz Burstable Pipelined Read Interface With Programmable Latency, Length, and Order 10000 Program/Erase Cycles Thre...
4194304-BIT: Features: Organization 512K-Byte Main Array 24K-Byte Protected Overlay-Block User-Defined x16 or x32 Data Bus Read Transfer Data Rates Up to 100 MBytes/s at Bus Frequencies Up to 40 MHz Burstable P...
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Supply voltage range, VDDI (5 V) (see Note 17) . . . ..............0.5 V to 7 V
Supply voltage range, VDDE (3.3 V) (see Note 17) . ............0.5 V to 4.6 V
Input voltage range, VI (except VPP) . . . . . . . . . . .0.5 V to VDDE + 0.5 V
Input voltage range, VI (VPP) . . . . . . . . . . . . . . . . . . . .........0.5 V to 14 V
Biased junction Temperature, TJ . . . . . . . . . . . . . . . . . ......................150C
Ambient temperature, TA . . . . . . . . . . . . . . . . . . . . . . .
(L) . . . . . . . . . . . . . . 40 V to 85°C
(E) . . . . . . . . . . . .40 V to 125°C
(Q) . . . . . . . . . . . . .55C to 150C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . ...................225C .
Soldering temperature, TSO (IR reflow for 180 seconds)
Soldering temperature (maximum ramp rate) . . . . . . ..........................6 C/s
Thermal resistance, QJA (junction-to-ambient) . . . . ......................50C/W
Data retention (at 55C ambient) . . . . . . . . . . . . . . . . .20 Years (minimum)
Number of erase/write cycles . . . . . . . . . . . . . . . . . . . ...........10000 Cycles
DescriptionThe TMS28F033 is the first synchronous nonvolatile flash memory device to offer a configurable burst interface to 16/32-bit microprocessors and microcontrollers operating at frequencies up to 40 MHz.
The TMS28F033 contains 4M bits of main memory that is user-configurable as either three or four independently erasable blocks. In addition to the main memory array, there is a protected overlay memory block that is normally hidden from the memory address map. The following table shows the three- and four-block main-memory-array configurations for both 16-bit and 32-bit data bus widths.