40890

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time or 4ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 150mV. 3. Ambient Temperature under DC Bias. No AC conditions. Chip Deselected.

The IDT70V5388/78 is a high-speed 64/32Kx18 bit synchronous FourPort RAM. The memory array utilizes FourPort memory cells to allow simultaneous access of any address from all four ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register and integrated burst counters, the IDT70V5388/78 has been optimized for applications having unidirectional or bi-directional data flow in bursts.

An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode.

The IDT70V5388/78 provides a wide range of functions specially designed to facilitate system operations. These include full-boundary, maskable address counters with associated interrupts for each port, mailbox interrupt flags on each port to facilitate inter-port communications, Memory Built-In Self-Test (MBIST), JTAG support and an asynchronous Master Reset to simplify device initialization. In addition, the address lines of IDT70V5388/78 have been set up as I/O pins, to permit the support of CNTRD (the ability to output the current value of the internal address counter on the address lines) and MKRD (the ability to output the current value of the counter mask register).

For specific details on the IDT70V5388/78 operation, please refer to the Functional Description and subsequent explanatory sections, beginning on page 21.