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40881

Features: IDT70V25 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave BUSY and Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of ...

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40881: Features: IDT70V25 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY inp...

40881 Data Sheet

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Part Number:
40881
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/6/11

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Product Details

Description



Features:

IDT70V25 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device
M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave
BUSY and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signalingbetween ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in 84-pin PGA, 84-pin PLCC and 100-pin TQFP
Industrial temperature range (-40°C to +85°C) is available for selected speeds
True Dual-Ported memory cells which allow simultaneous reads of the same memory location
High-speed access
Commercial: 15/20/25/35/55ns (max.)
Industrial: 20/25/35/55ns (max.)
 Low-power operation
IDT70V25S
Active: 400mW (typ.)
Standby: 3.3mW (typ.)
IDT70V25L
Active: 380mW (typ.)
Standby: 660 µW (typ.)
Separate upper-byte and lower-byte control for multiplexed bus compatibility


Pinout

Connection Diagram
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J84-1 package body is approximately 1.15 in x 1.15 in x .17 in.
PN100-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.


Specifications

Symbol
Rating
Commercial
& Industrial
Unit
VTERM
Terminal Voltage
with respect to GND
-0.5 to +7.0
V
VTER(2)
Terminal Voltage
-55 to +125
°C
TSTG
Temperature
Under Bias
-55 to +150
°C
IOUT
DC Output Current
50
mA

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.3V. 2944 tbl




Description

The IDT70V25 is a high-speed 8K x 16 Dual-Port Static RAM. The IDT70V25 is designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. This IDT70V25 provides two independent ports with separate control, reads or writes to any location in memory.

An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these IDT70V25 typically operate on only 400mW of power. The IDT70V25 is packaged in a ceramic 84-pin PGA, an 84-Pin PLCC and a 100-pin Thin Quad Flatpack.




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