4035B

The 4035B is a kind of fully synchronous edge-triggered 4-bit shift register with a clock input (CP), four synchronous parallel data inputs (P0-P3), two synchronous serial data inputs (J,K), a synchronous parallel enable input (PE), buffered parallel outputs from all 4-bit positions (Q0-Q3), a true/complement input (T/C) and an overriding asynchronous master reset input (MR).

There are some features of 4035B as follows: (1)typical shift frequency of 17 MHz at VDD=10 V; (2)J, K inputs to the first stage; (3)T/C input for true or complementary outputs; (4)synchronous parallel enable; (5)clock edge: triggered on low-to-high transition; (6)asynchronous master reset.

The last one is about the AC characteristics and set-up requirementsof 4035B: VSS=0 V, TA=25, CL=50 pF, RL=200 k, input transition times20 ns: (1)twCP at VDD=5 V, CP minimum pulse width: 125 ns min and 50 ns typ; (2)twCP at VDD=10 V, CP minimum pulse width: 55 ns min and 20 ns typ; (3)twCP at VDD=15 V, CP minimum pulse width: 44 ns min and 14 ns typ ; (4)twMR at VDD=5 V, MR minimum pulse width: 150 ns min and 60 ns typ; (5)twMR at VDD=10 V, MR minimum pulse width: 70 ns min and 25 ns typ; (6)twMR at VDD=15 V, MR minimum pulse width: 56 ns min and 20 ns typ.