3D7105

Features:

·  All-silicon, low-power CMOS technology
·  TTL/CMOS compatible inputs and outputs
·  Vapor phase, IR and wave solderable
·  Auto-insertable (DIP pkg.)
·  Low ground bounce noise
·  Leading- and trailing-edge accuracy
·  Delay range: .75 through 80ns
·  Delay tolerance: 5% or 1ns
·  Temperature stability: ±3% typical (0C-70C)
·  Vdd stability: ±1% typical (4.75V-5.25V)
·  Minimum input pulse width: 30% of total delay
·  14-pin DIP and 16-pin SOIC available as drop-in replacements for hybrid delay lines


Pinout

PIN DESCRIPTIONS
IN          Delay Line Input
O1         Tap 1 Output (20%)
O2         Tap 2 Output (40%)
O3         Tap 3 Output (60%)
O4         Tap 4 Output (80%)
O5         Tap 5 Output (100%)
VCC       +5 Volts
GND      Ground
N/C       No Connection

Specifications

PARAMETER	SYMBOL	MIN	MAX	UNITS	NOTES
DC Supply Voltage	VDD	-0.3	7.0	V
Input Pin Voltage	VIN	-0.3	VDD+0.3	V
Input Pin Current	IIN	-1.0	1.0	mA	25C
Storage Temperature	TSTRG	-55	150	C	10 sec
Lead Temperature	TLEAD		300	C

Description

CMOS integrated circuits. Each package contains a single delay line,tapped and buffered at 5 points spaced uniformly in time. Tap-to-tap (incremental) delay values can range from 0.75ns through 8.0ns. The input is reproduced at the outputs without inversion, shifted in time as per the user-specified dash number. The 3D7105 is TTL- and CMOScompatible,capable of driving ten 74LS-type loads, and features both rising- and falling-edge accuracy.

The all-CMOS 3D7105 integrated circuit has been designed as a reliable,economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 8-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC.