3D7010

Features:

• All-silicon, low-power CMOS technology*
• TTL/CMOS compatible inputs and outputs
• Vapor phase, IR and wave solderable
• Auto-insertable (DIP package)
• Low ground bounce noise
• Leading- and trailing-edge accuracy
• Delay range: 8 through 500ns
• Delay tolerance: 5% or 2ns
• Temperature stability: ±3% typical (0C-70C)
• Vdd stability: ±2% typical (4.75V-5.25V)
• Minimum input pulse width: 20% of total delay FUNCTIONAL DESCRIPTION


Pinout

PIN DESCRIPTIONS
IN            Delay Line Input
O1           Tap 1 Output (10%)
O2           Tap 2 Output (20%)
O3           Tap 3 Output (30%)
O4           Tap 4 Output (40%)
O5           Tap 5 Output (50%)
O6           Tap 6 Output (60%)
O7           Tap 7 Output (70%)
O8           Tap 8 Output (80%)
O9           Tap 9 Output (90%)
O10 Tap 10 Output (100%)
VDD +5 Volts
GND Ground

Specifications

PARAMETER	SYMBOL	MIN	MAX	UNITS	NOTES
DC Supply Voltage	VDD	-0.3	7.0	V
Input Pin Voltage	VIN	-0.3	VDD+0.3	V
Input Pin Current	IIN	-1.0	1.0	mA	25C
Storage Temperature	TSTRG	-55	150	C	10 sec
Lead Temperature	TLEAD		300	C

Description

The 3D7010 10-Tap Delay Line product family consists of fixed-delay CMOS integrated circuits. Each package contains a single delay line, tapped and buffered at 10 points spaced uniformly in time. Tap-to-tap (incremental) delay values can range from 8ns through 50ns. The input is reproduced at the outputs without inversion, shifted in time as per the user-specified dash number. The 3D7010 is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads, and features both rising- and falling-edge accuracy.

The all-CMOS 3D7010 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 14-pin auto-insertable DIP and a space saving surface mount 16-pin SOIC.