3D3215

Features:

· All-silicon, low-power 3.3V CMOS technology
· Vapor phase, IR and wave solderable
· Auto-insertable (DIP pkg.)
· Low ground bounce noise
· Leading- and trailing-edge accuracy
· Delay range: 1.5ns through 300ns
· Total delay tolerance: 2% or 0.5ns (3.3V, 25C)
· Temperature stability: ±1% typical (0C-70C)
· Vdd stability: ±1% typical (3.0V-3.6V)
· Static Idd: 1.3ma typical
· Minimum input pulse width: 25% of total delay


Pinout

PIN DESCRIPTIONS
IN                  Delay Line Input
O1                 Tap 1 Output (20%)
O2                 Tap 2 Output (40%)
O3                 Tap 3 Output (60%)
O4                 Tap 4 Output (80%)
O5                 Tap 5 Output (100%)
VDD               +3.3 Volts
GND               Ground
N/C                 No Connection

Specifications

PARAMETER	SYMBOL	MIN	MAX	UNITS	NOTES
DC Supply Voltage	VDD	-0.3	7.0	V
Input Pin Voltage	VIN	-0.3	VDD+0.3	V
Input Pin Current	IIN	-1.0	1.0	mA	25C
Storage Temperature	TSTRG	-55	150	C	10 sec
Lead Temperature	TLEAD		300	C

Description

The 3D3215 five-tap delay line architecture is shown in Figure 1. The delay line is composed of a number of delay cells connected in series.Each delay cell produces at its output a replica of the signal present at its input, shifted in time. The delay cells are matched and share the same compensation signals, which minimizes tap-to-tap delay deviations over temperature and supply voltage variations.