39K50

The 39K50 family, based on a 0.18-mm, six-layer metal,CMOS logic process, offers a wide range of high-density solutions at unparalleled system performance. The Delta39K family is designed to combine the high speed, predictable timing, and ease of use of CPLDs with the high densities and low power of FPGAs. With devices ranging from 30,000 to 200,000 usable gates, the family features devices ten times the size of previously available CPLDs. Even at these large densities, the Delta39K family is fast enough to implement a fully synthesizable 64-bit, 66-MHz PCI core.

The 39K50 is based on Logic Block Clusters (LBC) that are connected by Horizontal and Vertical (H and V) routing channels. Each LBC features eight individual Logic Blocks (LB) and two cluster memory blocks. Adjacent to each LBC is a channel memory block, which can be accessed directly from the I/O pins. Both types of memory blocks are highly configurable and can be cascaded in width and depth. See Figure 1 for a block diagram of the Delta39K architecture.

All the members of the Delta39K family have Cypress's highly regarded In-System Reprogrammability (ISR) feature, which simplifies both design and manufacturing flows, thereby reducing costs. The ISR feature provides the ability to recon- figure the devices without having design changes cause pinout or timing changes in most cases. The Cypress ISR function is implemented through a JTAG-compliant serial interface. Data is shifted in and out through the TDI and TDO pins respectively. Superior routability, simple timing, and the ISR allows users to change existing logic designs while simultaneously fixing pinout assignments and maintaining system performance.

The 39K50 family features JTAG for ISR and boundary scan, and is compatible with the PCI Local Bus specification, meeting the electrical and timing requirements. The Delta39K family also features user programmable bus-hold and slew rate control capabilities on each I/O pin.