39K165

• High density
-30K to 200K usable gates
-512 to 3072 macrocells
-136 to 428 maximum I/O pins
-Twelve dedicated inputs including four clock pins,four global I/O control signal pins and four JTAG interface pins for boundary scan and reconfigurability
• Embedded memory
-80K to 480K bits embedded SRAM
• 16K to 96K bits of (dual-port) channel memory
• High speed 233-MHz in-system operation
• AnyVolt™interface
-3.3V, 2.5V,1.8V, and 1.5V I/O capability
• Low-power operation
-0.18-mm six-layer metal SRAM-based logic process
-Full-CMOS implementation of product term array
-Standby current as low as 5mA
• Simple timing model
-No penalty for using full 16 product terms/macrocell
-No delay for single product term steering or sharing
• Flexible clocking
-Spread Aware™ PLL drives all four clock networks
• Allows 0.6% spread spectrum input clocks
• Several multiply, divide and phase shift options
-Four synchronous clock networks per device
-Locally generated product term clock
-Clock polarity control at each register
• Carry-chain logic for fast and efficient arithmetic operations
• Multiple I/O standards supported
-LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+
• Compatible with NOBL™, ZBT™, and QDR™ SRAMs
• Programmable slew rate control on each I/O pin
• User-programmable Bus Hold capability on each I/O pin
• Fully 3.3V PCI-compliant (to 66-MHz 64-bit PCI spec,rev. 2.2)
• CompactPCI hot swap ready
• Multiple package/pinout offering across all densities
-208 to 676 pins in PQFP, BGA, and FBGA packages
-Simplifies design migration across density
-Self-Boot™ solution in BGA and FBGA packages
• In-System Reprogrammable™ (ISR™)
-JTAG-compliant on-board programming
-Design changes do not cause pinout changes
• IEEE1149.1 JTAG boundary scan

The 39K165 family, based on a 0.18-mm, six-layer metal CMOS logic process, offers a wide range of high-density solutions at unparalleled system performance. The Delta39K family is designed to combine the high speed, predictable timing, and ease of use of CPLDs with the high densities and low power of FPGAs. With devices ranging from 30,000 to 200,000 usable gates, the family features devices ten times the size of previously available CPLDs. Even at these large
densities, the Delta39K family is fast enough to implement a fully synthesizable 64-bit, 66-MHz PCI core.

The 39K165 is based on Logic Block Clusters (LBC) that are connected by Horizontal and Vertical (H and V) routing channels. Each LBC features eight individual Logic Blocks (LB) and two cluster memory blocks. Adjacent to each LBC is a channel memory block, which can be accessed directly from the I/O pins. Both types of memory blocks are highly configurable and can be cascaded in width and depth. See Figure 1 for a block diagram of the Delta39K architecture.

All the members of the 39K165 family have Cypress's highly regarded In-System Reprogrammability (ISR) feature, which simplifies both design and manufacturing flows, thereby reducing costs. The ISR feature provides the ability to recon-figure the devices without having design changes cause pinout or timing changes in most cases. The Cypress ISR function is implemented through a JTAG-compliant serial interface. Data is shifted in and out through the TDI and TDO pins respectively. Superior routability, simple timing, and the ISR allows users to change existing logic designs while simultaneously fixing pinout assignments and maintaining system performance.

The entire family features JTAG for ISR and boundary scan, and is compatible with the PCI Local Bus specification, meeting the electrical and timing requirements. The Delta39K family also features user programmable bus-hold and slew rate control capabilities on each I/O pin.