38K100

The 38K100 family, based on a 0.18-mm, six-layer metal CMOS logic process, offers a wide range of solutions at very high system performance. With devices ranging from 512 to 1536 macrocells, Quantum38K is the highest density CPLD in the market besides Cypress's Delta39K. Specifically designed to address high-volume communication applications, this family also integrates Cypress's dual-port memory technology onto a CPLD.

The 38K100 is based on Logic Block Clusters (LBC) that are connected by Horizontal and Vertical (H&V) routing channels. Each LBC features eight individual Logic Blocks (LB). Adjacent to each LBC is a channel memory block, which can be accessed directly from the I/O pins. These channel memory blocks are highly configurable and can be cascaded in width and depth. See Figure 1 for a block diagram of the Quantum38K architecture.

All the members of the 38K100 family have Cypress's highly regarded In-System Reprogrammability (ISR) feature, which simplifies both design and manufacturing flows, thereby reducing costs. The ISR feature provides the ability to reconfigure the devices without having design changes cause pinout or timing changes in most cases. The Cypress ISR function is implemented through a JTAG-compliant serial interface. Data is shifted in and out through the TDI and TDO pins respectively. Superior routability, simple timing, and the ISR allows users to change existing logic designs while simultaneously fixing pinout assignments and maintaining system performance.

The 38K100 features JTAG for ISR and boundary scan, and is compatible with the PCI Local Bus specification, meeting the electrical and timing requirements. The Quantum38K family also features user programmable bus-hold and slew rate control capabilities on each I/O pin.