38054

At the heart of the STPC Consumer-S 38054 is an ad- vanced 64-bit processor block, dubbed the 38054. The 38054 includes a 5th generation processor core along with a 64-bit SDRAM con- troller, advanced  64-bit accelerated graphics and video controller, a high speed PCI local-bus con-troller and Industry standard PC chip set functions (Interrupt controller, DMA Controller, Interval timer and ISA bus).

The STPC Consumer-S 38054 makes use of a tightly coupled Unified Memory Architecture (UMA),where the same memory array is used for CPU main memory and graphics frame-buffer. This means a reduction in total system memory for sys- tem performances that are equal to that of a com-parable Frame Buffer and system memory based system, and generally much better, due to the higher memory bandwidth allowed by attaching the graphics engine directly to the 64-bit proces-sor host interface running at the speed of the proc- essor bus rather than the traditional PCI bus.

The 64-bit wide memory array provides the sys-tem with 528MB/s peak bandwidth. This allows for higher resolution screens and greater color depth.

The 'standard' PC chipset functions (DMA, inter-rupt controller, timers, power management logic)are integrated together with the x86 processor core; additional functions such as communica-tions ports are accessed by the STPC Consumer-S via internal ISA bus.

The PCI bus is the main data communication link to the STPC Consumer-S chip. The STPC Con-sumer-S 38054 translates appropriate host bus I/O and Memory cycles onto the PCI bus. It also supports generation of Configuration cycles on the PCI bus.

The STPC Consumer-S, as a PCI bus agent (host bridge class), fully complies with PCI specification 2.1. The chip-set also implements the PCI manda-tory header registers in Type 0 PCI configuration space for easy porting of  PCI aware system BI-OS. The device contains a PCI arbitration function for three external PCI devices.