38052

At the heart of the STPC Client 38052 is an advanced processor block, dubbed the ST X86. The 38052 includes a powerful x86 processor core along with a 64-bit DRAM controller, advanced 64bit acceler- ated graphics and video controller, a high speed PCI local-bus controller and Industry standard PC chip set functions (Interrupt controller, DMA Con-troller, Interval timer and ISA bus) and EIDE con-troller.

The STPC Client 38052 has in addition to the 5ST86 a Video subsystem and high quality digital Televi- sion output.

The STMicroelectronics x86 processor core is em- bedded with standard and application specific pe- ripheral modules on the same silicon die. The core has all the functionality of the ST Microelectronics standard x86 processor products, including the low power System Management Mode (SMM).

System Management Mode (SMM) 38052 provides an additional interrupt and address space that can be used for system power management or software transparent emulation of peripherals. While run-ning in isolated SMM address space, the SMM in-terrupt routine can execute without interfering with the operating system or application programs.

Further power management facilities include a suspend mode that can be initiated from either hardware or software. Because of the static nature of the core, no internal data is lost.

The STPC Client 38052 makes use of a tightly coupled Unified Memory Architecture (UMA), where the same memory array is used for CPU main memo- ry and graphics frame-buffer. This significantly re- duces total system memory with system perform- ances equal to that of a comparable solution with separate frame buffer and system memory. In ad- dition, memory bandwidth is improved by attach- ing the graphics engine directly to the 64-bit proc- essor host interface running at the speed of the processor bus rather than the traditional PCI bus.

The 64-bit wide memory array provides the sys-tem with 320MB/s peak bandwidth, double that of an equivalent system using 32 bits. This allows for higher screen resolutions and greater colour depth. The processor bus runs at the speed of the processor (DX devices) or half the speed (DX2 de- vices).

The 'standard' PC chipset functions (DMA, inter- rupt controller, timers, power management logic) are integrated with the x86 processor core.

The PCI bus is the main data communication link to the STPC Client chip. The STPC Client trans- lates appropriate host bus I/O and Memory cycles onto the PCI bus. It also supports the generation of Configuration cycles on the PCI bus. The STPC Client, as a PCI bus agent (host bridge class), fully complies with PCI specification 2.1. The chip-set also implements the PCI mandatory header regis- ters in Type 0 PCI configuration space for easy porting of PCI aware system BIOS. The device contains a PCI arbitration function for three exter- nal PCI devices.

The STPC Client 38052 integrates an ISA bus controller.Peripheral modules such as parallel and serial communications ports, keyboard controllers and  aditional ISA devices can be accessed by the STPC Client chip set through this bus.

An industry standard EIDE (ATA 2) controller is built into the STPC Client and connected internally via the PCI bus. 

Graphics functions are controlled by the on-chip SVGA controller and the monitor display is man-aged by the 2D graphics display engine.

This Graphics Engine is tuned to work with the host CPU to provide a balanced graphics system with a low silicon area cost. It performs limited graphics drawing operations, which include hard- ware acceleration of text, bitblts, transparent blts and fills. These operations can operate on off- screen or on-screen areas. The frame buffer size is up to 4 MBytes anywhere in the physical main memory.

The graphics resolution supported is a maximum of 1280x1024 in 65536 colours at 75Hz refresh rate and is VGA and SVGA compatible. Horizontal timing fields are VGA compatible while the vertical fields are extended by one bit to accommodate above display resolution.

STPC Client provides several additional functions to handle MPEG or similar video streams. The Video Input Port accepts an encoded digital video stream in one of a number of industry standard formats, decodes it, optionally decimates it by a factor of 2:1, and deposits it into an off screen area of the frame buffer. An interrupt request can be generated when an entire field or frame has been captured.

The video output pipeline incorporates a video- scaler and colour space converter function and provisions in the CRT controller to display a video window. While repainting the screen the CRT con- troller fetches both the video as well as the normal non-video frame buffer in two separate internal FIFOs (256-Bytes each). The video stream can be colour-space converted (optionally) and smooth scaled. Smooth interpolative scaling in both hori-zontal and vertical direction are implemented. Col-our and Chroma key functions are also imple-mented to allow mixing video stream with non-vid-eo frame buffer.

The video output passes directly to the RAMDAC for monitor output or through another optional col- our space converter (RGB to 4:2:2 YCrCb) to the programmable anti-flicker filter. The flicker filter is configured as either a two line filter with gamma correction (primarily designed for DOS type text) or a 3 line flicker filter (primarily designed for Win- dows type displays). The flicker filter is optional and can be software disabled for use with large screen area's of video.

The Video output pipeline of the STPC Client in-terfaces directly to the external digital TV encoder (STV0119). It takes a 24 bit RGB non-interlaced pixel stream and converts to a multiplexed 4:2:2 YCrCb 8 bit output stream, the logic includes a progressive to interlaced scan converter and logic to insert appropriate CCIR656 timing reference codes into the output stream. It facilitates the high quality display of VGA or full screen video streams received via the Video input port to standard NTSC or PAL televisions.

The STPC Client core is compliant with the Ad- vanced Power Management (APM) specification to provide a standard method by which the BIOS can control the power used by personal comput-ers. The Power Management Unit module (PMU) controls the power consumption by providing a comprehensive set of features that control the power usage and supports compliance with the United States Environmental Protection Agency's Energy Star Computer Program. The PMU pro-vides following hardware structures to assist the software in managing the power consumption by the system.

- System Activity Detection.
- 3 power-down timers detecting system inactivity:
   - Doze timer (short durations).
   - Stand-by timer (medium durations).
   - Suspend timer (long durations).
- House-keeping activity detection.
- House-keeping timer to cope with short bursts of house-keeping activity while dozing or in stand-by state.
- Peripheral activity detection.

- Peripheral timer detecting peripheral inactivity
- SUSP# modulation to adjust the system per-formance in various power down states of the sys-tem including full power on state.

- Power control outputs to disable power from dif-ferent planes of the board.

Lack of system activity for progressively longer period of times is detected by the three power down timers. These timers can generate SMI in-terrupts to CPU so that the SMM software can put the system in decreasing states of power con-sumption. Alternatively, system activity in a power down state can generate SMI interrupt to allow the software to bring the system back up to full power on state. The chip-set supports up to three power down states: Doze state, Stand-by state and Sus-pend mode. These correspond to decreasing lev-els of power savings.

Power down puts the STPC Client into suspend mode. The processor completes execution of the current instruction, any pending decoded instruc-tions and associated bus cycles. During the sus-pend mode, internal clocks are stopped.   remov-ing power down, the processor resumes instruc-tion fetching and begins execution in the instruc-tion stream at the point it had stopped.

A reference design for the STPC Client is availa-ble including the schematics and layout files, the design is a PC ATX motherboard design. The de- sign is available as a demonstration board for ap-plication and system development.

The STPC Client is supported by several BIOS vendors, including the super I/O device used in the reference design. Drivers for 2D accelerator,video features and EIDE are available on various operating systems.

The STPC Client has been designed using mod-ern reusable modular design techniques, it is pos-sible to add to or remove the standard features of the STPC Client or other variants of the 5ST86 family. Contact your local STMicroelectonics sales office for further information.