37940

The NAND Flash 37940 528 Byte/ 264 Word Page is a family of non-volatile Flash memories that uses NAND cell technology. The devices range from 128Mbits to 1Gbit and operate with either a 1.8V or 3V voltage supply. The size of a Page is either 528 Bytes (512 + 16 spare) or 264 Words (256 + 8 spare) depending on whether the device has a x8 or x16 bus width.

The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x8 or x16 Input/ Output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint.

Each block can be programmed and erased over 100,000 cycles. To extend the lifetime of NAND Flash devices it is strongly recommended to implement an Error Correction Code (ECC). A Write Protect pin is available to give a hardware protection against program and erase operations.

The 37940 feature an open-drain Ready/Busy output that can be used to identify if the Program/ Erase/Read (P/E/R) Controller is currently active. The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor.

A Copy Back command is available to optimize the management of defective blocks. When a Page Program operation fails, the data can be programmed in another page without having to resend the data to be programmed.

Each device has a Cache Program feature which improves the program throughput for large files. 37940 loads the data in a Cache Register while the previous data is transferred to the Page Buffer and  programmed into the memory array.

The 37940 is available in the following packages:

` TSOP48 12 x 20mm for all products

` VFBGA63 (8.5x15x1 mm, 6 x 8 ball array,0.8mm pitch) for the 512Mb product

` TFBGA63 (8.5x15x1.2 mm, 6 x 8 ball array, 0.8mm pitch) for the 1Gb product

` VFBGA63 (9x15x1 mm, 6 x 8 ball array, 0.8mm pitch) for 128Mb and 256Mb products. Three options are available for the NAND Flash family:

` Automatic Page 0 Read after Power-up, which allows the microcontroller to directly download the boot code from page 0.

` Chip Enable Don't Care, which allows code to be directly downloaded by a microcontroller, as Chip Enable transitions during the latency time do not stop the read operation.

` A Serial Number, which allows each device to be uniquely identified. The Serial Number options is subject to an NDA (Non Disclosure Agreement) and so not described in the datasheet. For more details of this option contact your nearest ST Sales office.

For information on how to order these options refer to Table 3, Ordering Information Scheme. Devices are shipped from the factory with Block 0 always valid and the memory content bits, in valid blocks,erased to '1'.

See Table 1, Product List, for all the devices available in the family.