37910

· Interface between LVTTL and GTLP logic levels
· Designed with edge rate control circuitry to reduceoutput noise in the GTLP port
· VREF pin provides external supply reference voltage for receiver threshold adjustability
· Special PVT compensation circuitry to provideconsistent performance over variations of process,supply voltage and temperature
· TTL compatible driver and control inputs
· Designed using Fairchild advanced BiCMOS technology
· Bushold data inputs on A Port to eliminate the need for external pull-up resistors for unused inputs
· Power up/down and power off high impedance for live insertion
· Open drain on GTLP to support wired-or connection
· Flow through pinout optimizes PCB layout
· A Port source/sink −24mA/+24mA
· B Port sink +50mA

The 37910 is a 1-bit bus buffer pair with separate bit paths, that provide LVTTL-to-GTLP and GTLP-to-LVTTL signal level translation. High speed backplane operation is a direct result of GTLP's reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3.

Fairchild's 37910 has internal edge-rate control and is process, voltage and temperature compensated. GTLP's I/O structure is similar to GTL and BTL but offers different output levels and receiver threshold. Typical GTLP output voltage levels are: V_OL = 0.5V, V_OH = 1.5V, and V_REF = 1V.