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36AB-300

Features: • Register-Register Late Write mode, Pipelined Read mode• 2.5 V +200/200 mV core power supply• 1.5 V or 1.8 V HSTL Interface• ZQ controlled programmable output drivers• Dual Cycle Deselect• Fully coherent read and write pipelines• Byte write oper...

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SeekIC No. : 004229054 Detail

36AB-300: Features: • Register-Register Late Write mode, Pipelined Read mode• 2.5 V +200/200 mV core power supply• 1.5 V or 1.8 V HSTL Interface• ZQ controlled programmable output driv...

36AB-300 Data Sheet

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Part Number:
36AB-300
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/24

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Product Details

Description



Features:

• Register-Register Late Write mode, Pipelined Read mode
• 2.5 V +200/200 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• ZQ controlled programmable output drivers
• Dual Cycle Deselect
• Fully coherent read and write pipelines
• Byte write operation (9-bit bytes)
• Differential HSTL clock inputs, K and K
• Asynchronous output enable
• Sleep mode via ZZ
• IEEE 1149.1 JTAG-compliant Serial Boundary Scan
• JEDEC-standard 119-bump BGA package
• Pb-Free 119-bump BGA package available


Specifications

Symbol
Description
Value
Unit
VDD
Voltage on VDD Pins
0.5 to 3.6
V
VDDQ
Voltage in VDDQ Pins
0.5 to VDD
V
VI/O
Voltage on I/O Pins
0.5 to VDDQ + 0.5 ( 3.6 V max.)
V
VIN
Voltage on Other Input Pins
0.5 to VDDQ + 0.5 ( 3.6 V max.)
V
IIN
Input Current on Any Pin
+/20
mA dc
IOUT
Output Current on Any I/O Pin
+/20
mA dc
TJ
Maximum Junction Temperature
125
TSTG
Storage Temperature
55 to 125
Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component.


Description

Because 36AB-300 are synchronous devices, address data inputs and read/write control inputs are captured on the rising edge of the input clock. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.

36AB-300 support pipelined reads utilizing a rising-edge-triggered output register. They also utilize a Dual Cycle Deselect (DCD) output deselect protocol.

36AB-300 are implemented with high performance technology and are packaged in a 119-bump BGA.




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