Features: SpecificationsDescription The 2SK2371/2SK2372 is N-Channel MOS Field Effect Transistor designed for high voltage switching applications.The 2SK2371/2SK2372 has 3 features including Low on-resistance,2SK2367: RDS(ON) = 0.25 (VGS = 13 V, ID = 10 A),2SK2368: RDS(ON) = 0.27 (VGS = 13 V, ID...
2SK2371/2SK2372: Features: SpecificationsDescription The 2SK2371/2SK2372 is N-Channel MOS Field Effect Transistor designed for high voltage switching applications.The 2SK2371/2SK2372 has 3 features including Low on-...
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Features: High Speed SwitchingLow On-ResistanceNo Secondary BreakdownLow Driving PowerHigh Voltage...
Features: - High Speed Switching- Low On-Resistance- No Secondary Breakdown- Low Driving Power- Hi...
The 2SK2371/2SK2372 is N-Channel MOS Field Effect Transistor designed for high voltage switching applications.The 2SK2371/2SK2372 has 3 features including Low on-resistance,2SK2367: RDS(ON) = 0.25 (VGS = 13 V, ID = 10 A),2SK2368: RDS(ON) = 0.27 (VGS = 13 V, ID = 10 A);Low Ciss Ciss = 3600 pF TYP; High Avalanche Capability Ratings.
The absolute maximun ratings of the 2SK2371/2SK2372 are at Ta=25°C, Drain to source voltage(2SK2371/2SK2372 ) VDSS is 450/500V;Gate to source voltage VGSS is ±30V;drain Current ID(DC) is ±25A;total power dissipation is 160W;channel temperature is 150°C maxnimum;Storage temperature is -55 to +150°C.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.Within each processing element is a set of computational units. The computational units consist of an arith- metic/logic unit (ALU), multiplier, and shifter. These units perform single-cycle instructions. The three units within each processing element are arranged in parallel, maximiz- ing computational throughput. Single multifunction instructions execute parallel ALU and multiplier opera- tions. In SIMD mode, the parallel ALU and multiplier operations occur in both processing elements. These com- putation units support IEEE 32-bit single-precision floating-point, 40-bit extended precision floating-point, and 32-bit fixed-point data formats. The addresses must be held valid throughout the cycle. CE and WE must return inactive for a minimum of tWR prior to the initiation of a subsequent read or write cycle. Data in must be valid tDS prior to the end of the write and remain valid for tDH afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low, the data bus can become active with read data defined by the address inputs. A low transition on WE will then disable the outputs tWEZ after WE goes active.
The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device is actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device.
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