Features: SpecificationsDescription The 2SD2527 is a silicon NPN triple diffusion plannar transistor designed for power amplification with high forward current transfer ratio.The 2SD2527 has 3 features including High foward current transfer ratio hFE;Satisfactory linearity of foward current transf...
2SD2527: Features: SpecificationsDescription The 2SD2527 is a silicon NPN triple diffusion plannar transistor designed for power amplification with high forward current transfer ratio.The 2SD2527 has 3 featu...
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The 2SD2527 is a silicon NPN triple diffusion plannar transistor designed for power amplification with high forward current transfer ratio.The 2SD2527 has 3 features including High foward current transfer ratio hFE;Satisfactory linearity of foward current transfer ratio hFE;Full-pack package which can be installed to the heat sink with one screw.
The absolute maximun ratings of the 2SD2527 are at Ta=25°C, Collecto to Base Voltage VCBO is 80V;Collector to Emitter Voltage VCEO is 60V;Emitter to Base Voltage VEBO is 6 V;Collector Current IC is 4A;collector power dissipation is 40 W(Tc=25°C);Junction temperature 150°C maxnimum;Storage temperature is -55 to +150°C.
The 2SD2527 is a true single-chip quad Ethernet interface solution, incorporating all analog and digital circuitry needed for a complete Ethernet front end circuit. It includes high-performance on- chip filtering, eliminating the need for external filters. In addition, the 2SD2527 supports the latest IEEE Ethernet features including full duplex and Auto-Negotiation. Information furnished by Analog Devices is believed to be accurate and reliable. How- ever, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the device has been deselected. The flange mounting arrangement provides a convenient assembly method, and the sturdy .187 shaft diameter permits the heavier loading frequently encountered where pulleys or belt drives are employed. The output bearing is fitted with a seal to help prevent the contamination that can occur in industrial applications.
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