2SD2467

      The 2SD2467 is a silicon NPN epitaxial planer type transistor designed For power switching .The 2SD2467 has 4 feature,that is,Low collector to emitter saturation voltage VCE(sat);Satisfactory linearity of foward current transfer ratio hFE;Large collector current IC;Full-pack package with outstanding insulation, which can be installed to the heat sink with one screw.
      The absolute maximun ratings of the 2SD2467 at Ta=25°C unless otherwise noted having Collector to base Voltage VCBO is 50V;Collector to emitter Voltage VCEO is 40 V;Emitter to base Voltage VEBO is 5V;Collector Current (DC)IC is 10A;Junction temperature is +150°C ;Storage temperature is -55 to +150°C ;collector power Dissipation Pc(Tc=25°C) is 40W ;Peak collector current ICP is 20A etc.  
      Applies to a single 2SD2467 without VCC supply, attached to a 1-Wire line. The earliest recognition of a negative edge is possible at tREH after VTH has been previously reached. Highlighted numbers are NOT in compliance with legacy 1-Wire product standards. See comparison table. Interval during the negative edge on IO at the beginning of a Presence Detect pulse between the time at which the voltage is 80% of VPUP and the time at which the voltage is 20% of VPUP. e represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. d represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input high threshold of the bus master. EPROM For Storage Of User-Programmable Configuration Data Factory-Programmed Unique 64-Bit Identification Number Bus-Interface Architecture Allowing Multiple bq2022s Attached to a Single Host Single-Wire Interface to Reduce Circuit Board Routing Synchronous Communication Reduces Host Interrupt Overhead No Standby Power Required Available in a 3-Pin SOT23 Package.Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. Schmitt-trigger input circuitry (TTL hysteresis) for B input allows jitter-free triggering from inputs with transition at rates as slow as 1 V/s, providing the circuit with excellent noise immunity, typically of 1.2 V. A high immunity to VCC noise, typically of 1.5 V, also is provided by internal latching circuitry.
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