Features: SpecificationsDescription The 2SD2403Q is a plastic-encapsulate transistor,and it has 2 features, one is NPN Silicon Epitaxial Planar Transistor for switching and amplifier applications;the other is This transistor is also available in the TO-223 case with the type designation PZT2403. T...
2SD2403Q: Features: SpecificationsDescription The 2SD2403Q is a plastic-encapsulate transistor,and it has 2 features, one is NPN Silicon Epitaxial Planar Transistor for switching and amplifier applications;th...
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The 2SD2403Q is a plastic-encapsulate transistor,and it has 2 features, one is NPN Silicon Epitaxial Planar Transistor for switching and amplifier applications;the other is This transistor is also available in the TO-223 case with the type designation PZT2403.
The absolute maximun ratings of the 2SD2403Q at Ta=25°C unless otherwise noted having Collector-base Voltage VCBO is 80V;Collector-emitter Voltage VCEO is 60 V;Emitter-base Voltage VEBO is 5.0 V;Collector Current (DC)IC is 3A;Junction temperature is +150°C ;Storage temperature is -55 to +150°C ;power Dissipation (at TA=25°C )Pc is 1.0 W etc.
The 2SD2403Q multirange, 12-bit data-acquisi- tion systems (DAS) require only a single +5V supply for operation, yet convert analog signals at their inputs up to 10V (MAX196) and 4V (MAX198). These systems provide six analog input channels that are indepen- dently software programmable for a variety of ranges: 10V, 5V, 0V to +10V, and 0V to +5V for the MAX196; VREF, VREF/2, 0V to +VREF, and 0V to +VREF/2 for the MAX198. This range switching increases the effec- tive dynamic range to 14 bits and provides the flexibility to interface 12V, 15V, and 4mA to 20mA powered sensors to a single +5V system. In addition, these con- verters are fault protected to 16.5V; a fault condition on any channel will not affect the conversion result of the selected channel. Other features include a 5MHz bandwidth track/hold, 100ksps throughput rate, soft- ware-selectable internal/external clock, internal/external acquisition control, 12-bit parallel interface, and internal 4.096V or external reference.
To reset internal circuitry at power-up; a logic 1 level is required at this pin for a duration of at least 2.5mS after the Xtal/Clock input and full VDD levels are applied. The component configuration shown in Figure 2 is recommended; for slow-rising power supplies the time constant of components should be increased accordingly.
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