Features: ` Single 3.0 V read, program and erase
Minimizes system level power requirements
` Compatible with JEDEC-standard commands
Uses same software commands as 2E PROMs
` Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP (I) (Package suffix: PFTN-Normal Bend Type, PFTR-Reversed Bend Type)
46-pin SON (Package suffix: PN)
48-pin CSOP (Package suffix: PCV)
48-ball FBGA (Package suffix: PBT)
` Minimum 100,000 program/erase cycles
` High performance
80 ns maximum access time
` Sector erase architecture
One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase
` Boot Code Sector Architecture
T = Top sector
B = Bottom sector
` Embedded Erase AlgorithmsTM
Automatically pre-programs and erases the chip or any sector
` Embedded program AlgorithmsTM
Automatically programs and verifies data at specified address
` Data Polling and Toggle Bit feature for detection of program or erase cycle completion
` Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
` Automatic sleep mode
When addresses remain stable, automatically switches themselves to low power mode
` Low VCC write inhibit 2.5 V
SpecificationsStorage Temperature.......................................................................................................55 to +125
Ambient Temperature with Power Applied .........................................................................40 to +85
Voltage with respect to Ground All pins except A9, OE, and RESET (Note 1)............0.5 V to +VCC +0.5 V
VCC (Note 1) ....................................................................................................................0.5 V to +5.5 V
A9, OE, and RESET (Note 2).............................................................................................0.5 V to +13.0 V
Notes:
1. Minimum DC voltage on input or l/O pins are 0.5 V. During voltage transitions, inputs may negative
overshoot VSS to 2.0 V for periods of up to 20 ns. Maximum DC voltage on output and l/O pins are VCC +0.5 V. During voltage transitions,outputs may positive overshoot to VCC +2.0 V for periods of up to 20 ns.
2. Minimum DC input voltage on A9, OE, and RESET pins are 0.5 V. During voltage transitions, A9, OE, and RESET pins may negative overshoot VSS to 2.0 V for periods of up to 20 ns. Maximum DC input voltage on A9, OE, and RESET pins are +13.0 V which may positive overshoot to 14.0 V for periods of up to 20 ns. Voltage difference between input voltage and supply voltage (VIN VCC) do not exceed 9 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
DescriptionThe MBM29LV160T/B is a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words
of 16 bits each. The MBM29LV160T/B is offered in a 48-pin TSOP (I), 46-pin SON, 48-pin CSOP and 48-ball FBGA packages. 2M8BIT is designed to be programmed in-system with the standard system 3.0 V VCC supply.
12.0 V VPP and 5.0 V VCC are not required for write or erase operations. 2M8BIT can also be reprogrammed
in standard EPROM programmers.
The standard MBM29LV160T/B offers access times of 80 ns and 120 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write
enable (WE), and output enable (OE) controls.
The MBM29LV160T/B is pin and command set compatible with JEDEC standard 2E PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
atch addresses and data needed for the programming and erase operations. Reading data out of 2M8BIT is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29LV160T/B is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margins. Typically, each sector can be programmed and verified in about 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margins.
Any individual sector is typically erased and verified in 1.0 second. (If already preprogrammed.) The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The MBM29LV160T/B is erased when shipped from the factory.
2M8BIT features single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automaticallyinhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been comleted, the device internally resets to the read mode.
The MBM29LV160T/B also has a hardware RESET pin. When this pin is driven low, execution of any Embedded
Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the
read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during
the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address locations being programmed or erased. These locations
need re-writing after the Reset. Resetting the device enables the system's microprocessor to read the boot-up
firmware from the Flash memory.
Fujitsu's Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiveness. The MBM29LV160T/B memory electrically erases all bits within
a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection.
2M8BIT Data Sheet
