28F001BX

` High-Integration Blocked Architecture
- One 8 KB Boot Block w/Lock Out
- Two 4 KB Parameter Blocks
- One 112 KB Main Block
` Simplified Program and Erase
- Automated Algorithms via On-Chip Write State Machine (WSM)
` SRAM-Compatible Write Interface
` Deep Power-Down Mode
- 0.05 A ICC Typical
- 0.8 A IPP Typical
` 12.0 V ±5% V<sub>PP</sub>
` High-Performance Read
- 120 ns, 150 ns Maximum Access Time
- 5.0 V ±10% VCC
` Hardware Data Protection Feature
- Erase/Write Lockout during Power Transitions
` Advanced Packaging, JEDEC Pinouts
- 32-Pin PDIP
- 32-Lead PLCC
` ETOX™ II Nonvolatile Flash Technology
- EPROM-Compatible Process Base
- High-Volume Manufacturing Experience

The Intel^® 28F001BX Flash Boot Block memory augments the nonvolatility, in-system electrical erasure and reprogrammability of Intel's flash memory by offering four separately erasable blocks and integrating a state machine to control erase and program functions. The specialized blocking architecture and automated programming of the 28F001BX provide a full-function, nonvolatile flash memory ideal for a wide range of applications, including PC boot/BIOS memory, minimum-chip embedded program memory and parametric data storage. The 28F001BX combines the safety of a hardware-protected 8-Kbyte boot block with the flexibility of three separately reprogrammable blocks (two 4-Kbyte parameter blocks and one 112-Kbyte code block) into one versatile, cost-effective flash memory. Additionally, reprogramming one block does not affect code stored in another block, ensuring data integrity.

The flexibility of flash memory reduces costs throughout the life cycle of a design. During the early stages of a system's life, flash memory reduces prototype development and testing time, allowing the system designer to modify in-system software electrically versus manual removal of components. During production, flash memory provides flexible firmware for just-in-time configuration, reducing system inventory and eliminating unnecessary handling and less reliable socketed connections. Late in the life cycle, when software updates or code "bugs" are often unpredictable and costly, flash memory reduces update costs by allowing the manufacturers to send floppy updates versus a technician. Alternatively, remote updates over a communication link are possible at speeds up to 9600 baud due to flash memory's fast programming time.

Reprogrammable environments, such as the personal computer, are ideal applications for the 28F001BX. The internal state machine provides SRAM-like timings for program and erasure, using the command and status registers. The blocking scheme allows BIOS update in the main and parameter blocks, while still providing recovery code in the boot block in the unlikely event a power failure occurs during an update, or where BIOS code is corrupted. Parameter blocks also provide convenient configuration storage, backing up SRAM and battery configurations. EISA systems, for example, can store hardware configurations in a flash parameter block, reducingsystem SRAM.

Laptop BIOS are becoming increasingly complex with the addition of power management software and extended system setup screens. BIOS code complexity increases the potential for code updates after the sale, but the compactness of laptop designs makes hardware updates very costly. Boot block flash memory provides an inexpensive update solution for laptops, while reducing laptop obsolescence. For portable PCs and hand-held equipment, the deep power-down mode dramatically lowers system power requirements during periods of slow operation or sleep modes.

The 28F001BX gives the embedded system designer several desired features. The internal state machine reduces the size of external code dedicated to the erase and program algorithms, as well as freeing the microcontroller or microprocessor to respond to other system requests during program and erasure. The four blocks allow logical segmentation of the entire embedded software: the 8-Kbyte block for the boot code, the 112-Kbyte block for the main program code and the two 4-Kbyte blocks for updatable parametric data storage, diagnostic messages and data, or extensions of either the boot code or program code. The boot block is hardware protected against unauthorized write or erase of its vital code in the field. Further, the power-down mode also locks out erase or write operations, providing absolute data protection during system power-up or power loss. This hardware protection provides obvious advantages for safety related applications such as transportation, military, and medical. The 28F001BX is well suited for minimum-chip embedded applications ranging from communications to automotive.

Operating Temperature
During Read................................. 0 °C to 70 °C⁽¹⁾
During Erase/Program................. 0 °C to 70 °C⁽¹⁾
Operating Temperature
During Read......................... 40 °C to +85 °C⁽²⁾
During Erase/Program....... .. 40 °C to +85 °C⁽²⁾
Temperature under Bias........ 10 °C to 80 °C ⁽¹⁾
Temperature under Bias...... 20 °C to +90 °C ⁽²⁾
Storage Temperature ...............65 °C to 125 °C
Voltage on Any Pin
(except A9, RP#, OE#, V_CC and V_PP)
with Respect to GND................. 2.0 V to 7.0 V⁽³⁾
Voltage on A9, RP#, and OE#
with Respect to GND.............2.0 V to 13.5 V^{(3, 4)}
VPP Program Voltage
with Respect to GND
During Erase/Program..........2.0 V to 14.0 V^{(3, 4)}
VCC Supply Voltage
with Respect to GND................. 2.0 V to 7.0 V⁽³⁾
Output Short Circuit Current ..................100 mA<sup>(5)

NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Operating temperature is for extended temperature product defined by this specification.
3. Minimum DC voltage is 0.5 V on input/output pins. During transitions, this level may undershoot to 2.0 V for periods <20 ns. Maximum DC voltage on input/output pins is V_CC +0.5 V which, during transitions, may overshoot to V_CC + 2.0 V for periods <20 ns.
4. Maximum DC voltage on A9 or VPP may overshoot to +14.0 V for periods <20 ns.
5. Output shorted for no more than one second. No more than one output shorted at a time.</sup>