2510CGLFT

Specifications

Package TSSOP 24 Speed NA Temperature C Voltage 3.3 V


Description

10 + 1 OUTPUTS 3.3V PHASE
The ICS2510C is a high performance, low skew, low jitter clock driver. ICS2510C uses a phase lock loop (PLL) technology to align, in both phase and frequency, the CLKIN signal with the CLKOUT signal. IICS2510C is specifically designed for use with synchronous SDRAMs. The ICS2510C operates at 3.3V VCC and drives up to ten clock loads.

One bank of ten outputs provide low-skew, low-jitter copies of CLKIN. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLKIN. Outputs can be enabled or disabled via control (OE) inputs. When the OE inputs are high, the outputs align in phase and frequency with CLKIN; when the OE inputs are low, the outputs are disabled to the logic low state.

The ICS2510C does not require external RC filter components. The loop filter for the PLL is included on chip, minimizing component count, board space, and cost. The test mode shuts off the PLL and connects the input directly to the output buffer. This test mode, the ICS2510C can be use as low skew fanout clock buffer device. The ICS2510C comes in 24 pin 173mil Thin Shrink Small-Outline package (TSSOP) package.

Meets or exceeds PC133 registered DIMM specification1.1

Spread Spectrum Clock Compatible

Distributes one clock input to one bank of ten outputs

Operating frequency 25MHz to 175MHz

External feedback input (FBIN) terminal is used to synchrionize the outputs to the clock input

No external RC network required

Operates at 3.3V Vcc

Plastic 24-pin 173mil TSSOP package