24010

` High-Performance Fixed-Point Digital Signal Processor (DSP) TMS320C62x
   4-, 3.33-ns Instruction Cycle Time
    250-, 300-MHz Clock Rate
   Eight 32-Bit Instructions/Cycle
   2000, 2400 MIPS
` C6203B and C6202/02B GLS Ball Grid Array (BGA) Packages are Pin-Compatible With the C6204 GLW BGA Package†
` VelociTI<sup>TM</sup> Advanced Very-Long-Instruction- Word (VLIW) C62x<sup>TM</sup> DSP Core
   Eight Highly Independent Functional Units:
   Six ALUs (32-/40-Bit)
   Two 16-Bit Multipliers (32-Bit Result)
   Load-Store Architecture With 32 32-Bit General-Purpose Registers
   Instruction Packing Reduces Code Size
   All Instructions Conditional
` Instruction Set Features
   Byte-Addressable (8-, 16-, 32-Bit Data)
   8-Bit Overflow Protection
   Saturation
   Bit-Field Extract, Set, Clear
   Bit-Counting
   Normalization
` 7M-Bit On-Chip SRAM
   3M-Bit Internal Program/Cache (96K 32-Bit Instructions)
   4M-Bit Dual-Access Internal Data (512K Bytes)
   Organized as Two 256K-Byte Blocks for Improved Concurrency
` 32-Bit External Memory Interface (EMIF)
   Glueless Interface to Synchronous Memories: SDRAM or SBSRAM
   Glueless Interface to Asynchronous Memories: SRAM and EPROM
   52M-Byte Addressable External Memory Space
` Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel
` Flexible Phase-Locked-Loop (PLL) Clock Generator
` 32-Bit Expansion Bus (XBus)
   Glueless/Low-Glue Interface to Popular PCI Bridge Chips
   Glueless/Low-Glue Interface to Popular Synchronous or Asynchronous Microprocessor Buses
   Master/Slave Functionality
   Glueless Interface to Synchronous FIFOs and Asynchronous Peripherals
` Three Multichannel Buffered Serial Ports (McBSPs)
   Direct Interface to T1/E1, MVIP, SCSA Framers
   ST-Bus-Switching Compatible
   Up to 256 Channels Each
   AC97-Compatible
   Serial-Peripheral Interface (SPI) Compatible (Motorola^TM )
` Two 32-Bit General-Purpose Timers
` IEEE-1149.1 (JTAG‡) Boundary-Scan-Compatible
` 352-Pin BGA Package (GNZ) (C6203C only)
` 384-Pin BGA Package (GLS) (C6203B only)
` 384-Pin BGA Package (GNY) [C6203B and C6203C]
` 0.12-m/6-Level Metal Process (C6203C)
` 0.15-m/5-Level Metal Process (C6203B)
   CMOS Technology
` 3.3-V I/Os, 1.2-V Internal (C6203C)
` 3.3-V I/Os, 1.5-V Internal (C6203B)

absolute maximum ratings over operating case temperature ranges (unless otherwise noted)†
Supply voltage range, CV_DD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  0.3 V to 1.8 V
Supply voltage range, DV_DD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.3 V to 4 V
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 4 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 4 V
Operating case temperature ranges, T_C:(default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 90
                                                                (A version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 to105
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 to 150
Temperature cycle range, (1000-cycle performance) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  40 to 125

† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to V_SS.

The TMS320C6203B and TMS320C6203C devices are part of the TMS320C62x^TM fixed-point DSP generation in the TMS320C6000^TM DSP platform. The C62x^TM DSP devices are based on the high-performance, advanced VelociTI^TM very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. The TMS320C62x^TM DSP offers cost-effective solutions to high-performance DSP-programming challenges.

The TMS320C6203B/03C has a performance capability of up to 2400 MIPS at a clock rate of 300 MHz. The C6203B/03C DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6203B/03C can produce two multiply-accumulates (MACs) per cycle for a total of 600 million MACs per second (MMACS). The C6203B/03C DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6203B/03C device program memory consists of two blocks, with a 256K-byte block configured as memory-mapped program space, and the other 128K-byte block user-configurable as cache or memory-mapped program space. Data memory for the C6203B/03C consists of two 256K-byte blocks of RAM.

The C6203B/03C device has a powerful and diverse set of peripherals. The peripheral set includes three multichannel buffered serial ports (McBSPs), two general-purpose timers, a 32-bit expansion bus (XBus) that offers ease of interface to synchronous or asynchronous industry-standard host bus protocols, and a glueless 32-bit external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.

The C62x^TM devices have a complete set of development tools which includes: a new C compiler, an assembly ptimizer to simplify programming and scheduling, and a Windows^TM debugger interface for visibility into source code execution.