2309-1HPGG

Specifications

Input Frequency 10-133 MHz No. of Inputs 1 Temperature C Output Frequency 10-133 MHz No. of Outputs 4 + 5 Voltage 3.3 V Package TSSOP 16 Speed NA Input 3.3 V LVTTL Output 3.3 V LVTTL Output Skew 0.25 ns Max Prop Delay 0.35 ns Jitter cycle-to-cycle 0.2 ns Type Zero Delay Buffer


Description

HI SPD PHASE LOCK LOOP
The ICS2309 is a low phase noise, high-speed PLLbased, low-skew zero delay buffer. Based on ICS'proprietary low jitter Phase Locked Loop (PLL)techniques, the device provides nine low skew outputs at speeds up to 133 MHz at 3.3 V. The outputs can be generated from the PLL (for zero delay), or directly from the input (for testing), and can be set to tri-state mode or to stop at a low level. The PLL feedback is on-chip and is obtained from the CLKOUT pad.

The ICS2309 is available in two different versions. The ICS2309-1 is the base part. The ICS2309-1H is a high drive version with faster rise and fall times.

Clock outputs from 10 to 133 MHz

Zero input-output delay

Nine low skew (<250 ps) outputs

Device-to-device skew <700 ps

Full CMOS outputs with 12 mA output drive capability at TTL levels

5 V tolerant CLKIN

Tri-state mode for board-level testing

Advanced, low power, sub-micron CMOS process

Operating voltage of 3.3 V

Industrial temperature range available

Packaged in 16-pin SOIC and TSSOP (-1H version only)

RoHS 5 (green) or RoHS 6 (green and lead free)complaint packaging