Features: `Low Voltage, Ultra Low Power Operation - Vcc = 2.7 to 3.6 V - Icc = 5 A (typical) at standby - Icc = 1.5 mA (typical) at 1 MHz - Meets JEDEC LV Interface Spec (JESD8-A) - 5 Volt tolerant inputs and I/O's`CMOS Electrically Erasable Technology - Superior factory testing - Reprogrammable i...
22LV10AZ -25: Features: `Low Voltage, Ultra Low Power Operation - Vcc = 2.7 to 3.6 V - Icc = 5 A (typical) at standby - Icc = 1.5 mA (typical) at 1 MHz - Meets JEDEC LV Interface Spec (JESD8-A) - 5 Volt tolerant ...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
Symbol |
Parameter |
Conditions |
Ratings |
Unit |
VCC | Supply Voltage | Relative to Ground |
-0.5 to +6.0 |
V |
VI,VO | Voltage Applied to Any Pin2 | Relative to Ground1 |
-0.5 to 5.5 |
V |
IO | Output Current | Per pin (IOL, IOH) |
±25 |
mA |
TST | Storage Temperature |
-65 to +150 |
||
TLT | Lead Temperature | Soldering 10 second |
+300 |
The PEEL™22LV10AZ is a Programmable Electrically Erasable Logic (PEEL™) SPLD (Simple Programmable Logic Device) that operates over the supply voltage range of 2.7V-3.6V and fea- tures ultra-low, automatic "zero" power-down operation. The PEEL™22LV10AZ is logically and functionally similar to Anachip's 5V PEEL™22CV10A+ and PEEL™22CV10AZ. The "zero power" (50 A max. Icc) power-down mode makes the PEEL™22LV10AZ ideal for a broad range of battery-powered portable equipment applications, from hand-held meters to PCMCIA modems. EE-reprogrammability provides both the convenience of fast reprogramming for product development and quick product personalization in manufacturing, including Engineering Change Orders.
The differences between the PEEL™22LV10AZ and PEEL™22CV10A include the addition of programmable clock polarity, p-term clock, and Schmitt trigger input buffers on all inputs, including the clock. Schmitt trigger inputs allow direct input of slow signals such as biomedical and sine waves or clocks. Like the PEEL™22CV10, the PEEL™22LV10AZ is a pin and JEDEC compatible, logical superset of the industry stan- dard PAL22V10 SPLD (Figure 26). The PEEL™22LV10AZ pro- vides additional architectural features that allow more logic to be incorporated into the design. The PEEL™22LV10AZ architecture allows it to replace over twenty standard 24-pin DIP, SOIC, TSSOP and PLCC packages.