21014

Features: SpecificationsDescriptionThe 21014 is a CMOS high speed 262,144 X 4 dynamic RAM optimized for high performance applications such as mainframes,graphics and microprocessor systems.The 21014 features fast page mode operation which allows high random access of memory cells within the same r...

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SeekIC No. : 004215327 Detail

21014: Features: SpecificationsDescriptionThe 21014 is a CMOS high speed 262,144 X 4 dynamic RAM optimized for high performance applications such as mainframes,graphics and microprocessor systems.The 21014...

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Part Number:
21014
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/25

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Product Details

Description



Features:






Specifications






Description

The 21014 is a CMOS high speed 262,144 X 4 dynamic RAM optimized for high performance applications such as mainframes,graphics and microprocessor systems.The 21014 features fast page mode operation which allows high random access of memory cells within the same row.Features of it are:(1)fast page mode operation;(2)single 5V+/-10% power supply;(3)512 cycles/8 ms refresh;(4)common I/O using "early write";(5)available in plastic DIP(P) and SOJ(T) packages.

The absolute maximum ratings of the 21014 can be summarized as:(1)voltage on any pin relative to Vss:-1V to +7.0V;(2)voltage on power supply relative to Vss:-1V to +7.0V;(3)storage temperature is -55 to +125;(4)power dissipation:600 mW;(5)short circuit output current:50 mA.And the recommended operating conditions are:(1)supply voltage:4.5 to 5.5 V;(2)ground:0 V;(3)input high voltage:2.4 to Vcc+1 V;(4)input low voltage:-1.0 to 0.8 V.

The 21014 contains 1,048,576 memory locations.Twenty address bits are required to address a particular memory location.since the 21014 has only 10 address input pins,time multiplexed addressing is uses to input 10 row and 10 column addresses.The multiplexing is controlled by the timing relationship between the row address strobe,the column address strobe and the valid row and column address inputs.






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