Features: IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL ROSSPOINT FAMILY
Advanced Architecture Addresses Programmabl Interconnect, Bus Interface Integration andJumper/Switch
Any Input to Any Output°± Rout
Fixed HIGH or LOW Output Option for Jumper/DI Switch Emulation
Space-Saving PQFP and BGA Packagin
Dedicated IEEE 1149.1-Compliant Boundary ScaTest
HIGH PERFORMANCE ECMOS TECHNOLOGY
3.3V Core Power Suppl
3.5ns Input-to-Output/3.5ns Clock-to-Output
250MHz Maximum Clock Frequency
TTL/3.3V/2.5V Compatible Input Thresholds a Output Levels (Individually Programmable)*
Low-Power: 16.5mA Quiescent Icc
24mA Drive with Programmable Slew RateOL Control Option
PCI Compatible Drive Capability
Schmitt Trigger Inputs for Noise Immunit
Electrically Erasable and Reprogrammabl
Non-Volatile CMOS Technology
ispGDXV OFFERS THE FOLLOWING ADVANTAGES
3.3V In-System Programmable Using Boundary Sca Test Access Port (TAP)
Change Interconnects in Second
FLEXIBLE ARCHITECTURE
Combinatorial/Latched/Registered Inputs or Output
Individual I/O Tri-state Control with Polarity Contro
Dedicated Clock/Clock Enable Input Pins (four) Programmable Clocks/Clock Enables from I/O Pins (40)
Programmable Wide-MUX Cascade Featur
Supports up to 16:1 MUX
Programmable Pull-ups, Bus Hold Latch and Ope Drain on I/O Pins
Outputs Tri-state During Power-up (°Live Insertio Friendly)
DESIGN SUPPORT THROUGH LATTICE°OS ispGD
DEVELOPMENT SOFTWARE
MS Windows or NT / PC-Based or Sun O/
asy Text-Based Design Entr
Automatic Signal Routin
Program up to 100 ISP Devices Concurrentl
Simulator Netlist Generation for Easy Board-Leve Simulation
Application The ispGDXV/VA Family architecture has been devel-oped to deliver an in-system programmable signal routing
solution with high speed and high flexibility. The devices arergeted for three similar but distinct classes of end-
system applications:SpecificationsSupply Voltage V cc................................ -0.5 to +5.4V
Input Voltage Applied..............................-0.5 to +5.6V
Off-State Output Voltage Applied............-0.5 to +5.6V
Storage Temperature.............................-65 to 150°C
Case Temp. with Power Applied.............-55 to 125°C
Max. Junction Temp. (Tj) with Power Applied.....150°CDescriptionThe ispGDXV/VA architecture provides a family of fast,flexible programmable devices to address a variety of ystem-level digital signal routing and interface requirements including:
Multi-Port Multiprocessor Interfaces
Wide Data and Address Bus Multiplexing
e.g. 16:1 High-Speed Bus MUX)
rogrammable Control Signal Routing
e.g. Interrupts, DMAREQs, etc.)
Board-Level PCB Signal Routing for Prototyping or
Programmable Bus Interfaces
The ispGDXV/VA feature fast operation, with input-to-output ignal delays (Tpd) of 3.5ns and clock-to-output delays of
3.5ns.
The architecture of the ispGDXV/VA consists of a series of rogrammable I/O cells interconnected by a Global Rout-
ing Pool (GRP). All I/O pin inputs enter the GRP directly are registered or latched so they can be routed to the
required I/O outputs. I/O pin inputs are defined as foursets (A,B,C,D) which have access to the four MUX inputs
160VA Data Sheet
