1524AM

Specifications Temperature C Voltage 3.3 V Package SOIC 24 Speed NA DescriptionDUAL OUPUT PHASE CONTROLLThe ICS1524 is a user programmable high performance phase locked loop...

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SeekIC No. : 004210428 Detail

1524AM: Specifications Temperature C Voltage 3.3 V Package SOIC 24 Speed NA Descr...

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Part Number:
1524AM
Supply Ability:
5000

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  • 1~5000
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  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/21

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Product Details

Description



Specifications

Temperature C Voltage 3.3 V Package SOIC 24 Speed NA


Description

DUAL OUPUT PHASE CONTROLL
The ICS1524 is a user programmable high performance phase locked loop (PLL) frequency synthesizer capable of generating single ended (SSTL) and differential (PECL) outputs up to 250 MHz from a variety of timing sources. A second set of outputs (DPACLK) may be phase offset from the main set (CLK) providing for dynamic adjustment in 5.6o to 22.5o steps through the full 360o. Phase adjustment is derived from a locked loop and therefore the delayed clock is phase stable relative to the main clock. The ICS1524 is a low-cost but very high-performance frequency generator. It is perfectly suited to general purpose phase controlled clock synthesis as well as line-locked and genlocked high-resolution video applications. Using ICS's advanced low-voltage CMOS mixed-mode technology, the ICS1524 is an effective phase controlled clock synthesizer and also supports video projectors and displays at resolutions from VGA to beyond UXGA. The advanced PLL ICS1524 uses either its internal programmable feedback divider or an external divider. The device available in a 24-pin wide small-outline integrated circuit (SOIC) package. Through use of the serial I2C bus, the ICS1524 may be user programmed into a wide range of timing generation applications. Programmed configuration as well as certain operating status can be monitored through the same I2C bus, making the device suitable for intelligent system designs.

ICS1524 features:

  • 250 MHz balanced PECL differential outputs
  • 150 MHz single-ended SSTL_3 clock outputs
  • Dynamic Phase Adjust (DPA) for DPACLK outputs
  • Software phase adjustment up to 160 MHz o 360
  • Adjustment at up to 1/64 clock increments
  • Wide input frequency range
  • 8 kHz to 100 MHz
  • External or internal loop filter selection
  • Uses 3.3 VDC
  • Inputs are 5 volt tolerant.
  • I2C-bus serial interface runs at either low speed (100 kHz) or high speed (400 kHz).
  • Hardware and Software PLL Lock detection Applications
  • General Purpose Frequency Synthesis
  • LCD Monitors and Video Projectors
  • Genlocking Multiple Video Subsystems
  • Communications Clock Generation
  • High Frequency Clock Generation



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