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128Mb DDR SDRAM

Features: • Double-data-rate architecture; two data transfers per clock cycle• Bidirectional data strobe(DQS)• Four banks operation• Differential clock inputs(CK and CK)• DLL aligns DQ and DQS transition with CK transition• MRS cycle with address key programs-. ...

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SeekIC No. : 004209084 Detail

128Mb DDR SDRAM: Features: • Double-data-rate architecture; two data transfers per clock cycle• Bidirectional data strobe(DQS)• Four banks operation• Differential clock inputs(CK and CK)̶...

128Mb DDR SDRAM Data Sheet

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Part Number:
128Mb DDR SDRAM
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/30

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Product Details

Description



Features:

• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM/DM for write masking only
• Auto & Self refresh
• 15.6us refresh interval(4K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II package


Pinout

Connection Diagram


Specifications

Parameter Symbol Value Unit
Voltage on any pin relative to VSS VIN, VOUT -0.5 ~ 3.6 V
Voltage on VDD supply relative to VSS VDD, VDDQ -1.0 ~ 3.6 V
Voltage on VDDQ supply relative to VSS VDDQ -0.5 ~ 3.6 V
Storage temperature TSTG -55 ~ +150 °C
Power dissipation PD 1.0 W
Short circuit current IOS 50 mA



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