1032EA

The ispLSI 1032EA is a High Density Programmable Logic Device containing 192 Registers, 64 Universal I/O pins, four Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1032EA features 5V in-system programmability (ISP™) and in-system diagnostic capabilities via IEEE 1149.1 Test Access Port. The device offers non-volatile reprogrammability ofthe logic, as well as the interconnects to provide truly reconfigurable systems. A functional superset of the architecture, the ispLSI 1032EA device adds user selectable 3.3V or 5V I/O and open drain output options.

The basic unit of logic on the ispLSI 1032EA device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1.D7 (Figure 1). There are a total of 32 GLBs in the ispLSI 1032EA device. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device.