1032E

Features:

* HIGH DENSITY PROGRAMMABLE LOGIC
  - 6000 PLD Gates
  - 64 I/O Pins, Eight Dedicated Inputs
  - 192 Registers
  - High Speed Global Interconnect
  - Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
  - Small Logic Block Size for Random Logic
* HIGH PERFORMANCE E² CMOS^(R)  TECHNOLOGY
   - fmax = 125 MHz Maximum Operating Frequency
   - tpd = 7.5 ns Propagation Delay
   - TTL Compatible Inputs and Outputs
   - Electrically Erasable and Reprogrammable
   - Non-Volatile
   - 100% Tested at Time of Manufacture
   - Unused Product Term Shutdown Saves Power
* ispLSI OFFERS THE FOLLOWING ADDED FEATURES
   - In-System Programmable (ISP(TM)) 5-Volt Only
   - Increased Manufacturing Yields, Reduced Time-to-Market and Improved Product Quality
   - Reprogram Soldered Devices for Faster Prototyping
* OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
   - Complete Programmable Device Can Combine Glue Logic and Structured Designs
   - Enhanced Pin Locking Capability
   - Four Dedicated Clock Input Pins
   - Synchronous and Asynchronous Clocks
   - Programmable Output Slew Rate Control to Minimize Switching Noise
   - Flexible Pin Placement
   - Optimized Global Routing Pool Provides Global Interconnectivity
* ispEXPERT^(TM) LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
   - Superior Quality of Results
   - Tightly Integrated with Leading CAE Vendor Tools
   - Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER^(TM)
   - PC and UNIX Platforms 


Pinout




Specifications

Supply Voltage V_cc .................................. -0.5 to +7.0V
Input Voltage Applied........................-2.5 to V_CC +1.0V
Off-State Output Voltage Applied .....-2.5 to V_CC +1.0V
Storage Temperature.................................-65 to 150
Case Temp. with Power Applied ................-55 to 125
Max. Junction Temp. (T_J) with Power Applied ... ...150
1. Stresses above  those listed  under  the "Absolute  Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).


Description

The ispLSI and pLSI 1032E are High Density Program-mable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedi-cated Clock Input pins and a Global Routing  Pool (GRP).The GRP provides complete interconnectivity between all of these elements. The features 5-Volt in-system programmability and in-system diagnostic ca-pabilities. The ispLSI 1032E device offers non-volatile reprogrammability of the logic, as well as the intercon-nects to provide truly reconfigurable systems. It is architecturally and parametrically compatible to the device, but multiplexes four input pins to control in-system programming. A functional superset of theispLSI and pLSI 1032 architecture, the ispLSI and pLSI 1032E devices add two new global output enable pins.
The basic unit of logic on the ispLSI and pLSI 1032E devices is the Generic Logic Block (GLB). The GLBs are labeled A0, A1.D7 (see Figure 1). There are a total of 32 GLBs in the ispLSI and pLSI 1032E devices. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device.