100E016

For applications which call for larger than 8-bit counters, multiple E016s can be tied together to achieve very wide bit width counters. The active low terminal count (TC*) output and count enable input (CE*) greatly facilitate the cascading of E016 devices. Two E016s can be cascaded without the need for external gating; however, for counters wider than 16 bits, external OR gates are necessary for cascade implementations.

Figure 3 below illustrates the cascading of 4 E016s to build a 32-bit high frequency counter. Note that the E101 gates are used to OR the terminal count outputs of the lower order E016s to control the counting operation of the higher order bits. When the terminal count of the preceding device (or devices) goes low (the counter reaches an all 1s state), the more significant E016 is set in its count mode and will count one binary digit upon the next positive clock transition.

In addition, the preceding devices will also count one bit, sending their terminal count outputs back to a high state, disabling the count operation of the more significant counters, and placing them back into hold modes. Therefore, for an E016 in the chain to count, all of the lower order terminal count outputs must be in the low state. The bit width of the counter can be increased or decreased by simply adding or subtracting E016 devices from Figure 3 and maintaining the logic pattern illustrated in the same figure.

The maximum frequency of operation for the cascaded counter chain is set by the propagation delay of the TC* output, the necessary setup time of the CE* input, and the propagation delay through the OR gate controlling it (for 16-bit counters the limitation is only the TC* propagation delay and the CE* setup time). Figure 3 shows EL01 gates used to control the count enable inputs; however, if the frequency of operation is lower, a lower ECL OR gate can be used. Using the worst case guarantees for these parameters, the maximum count frequency for a greater than 16-bit counter is 500 MHz, and for a 16-bit counter is 625 MHz. Note that this assumes the trace delay between the TC* outputs and the CE* inputs are negligible. If this is not the case, estimates of these delays need to be added to the calculations.

A single E016 can be used to divide by any ratio from 2 to 256 inclusive. If divide ratios of greater than 256 are needed, multiple E016s can be cascaded in a manner similar to that already discussed. When E016s are cascaded to build larger dividers, the TCLD pin will no longer provide a means for loading on terminal count.

Because one does not want to reload the counters until all of the devices in the chain have reached terminal count, external gating of the TC* pins must be used for multiple E016 divider chains.

Figure 6 shows a typical block diagram of a 32-bit divider chain. Once again, to maximize the frequency of operation, EL01 OR gates were used. For lower frequency applications, a slower OR gate could replace the EL01. Note that for a 16-bit divider, the OR function feeding the PE* (program enable) input CANNOT be placed by a wire OR tie as the TC* output of the least significant E016 must also feed the CE* input of the most significant E016. If the two TC* outputs were OR tied, the cascaded count operation would not operate properly. Because, in the cascaded form, the PE* feedback is external and requires external gating, the maximum frequency of operation will be significantly less than the same operation in a single device.

The SK10/100E016 is a high-speed synchronous, presettable, cascadable 8-bit binary counter.

The counter features 100E016 internal feedback of TC*, gated by the TCLD (terminal count load) pin. When TCLD is LOW (or left open, in which case it is pulled LOW by the internal pull-downs), the TC* feedback is disabled, and counting proceeds continuously, with TC* going LOW to indicate an all-one state. When TCLD is HIGH, the TC* feedback causes the counter to automatically reload upon TC* = LOW, thus functioning as a programmable counter. The Qn outputs do not need to be terminated for the count function to operate properly. To minimize noise and power, unused Q outputs should be left unterminated.