100354PC

Low Level Output Current :
Number of Circuits : 1
Polarity : Non-Inverting
Input Type : Single-Ended
Output Type : Single-Ended
Maximum Operating Temperature : + 85 C
Mounting Style : Through Hole
Propagation Delay Time : 3 ns
Logic Family : ECL
Logic Type : ECL
Packaging : Rail
Supply Voltage - Max : - 5.7 V
Package / Case : PDIP W
High Level Output Current : - 100 mA


Features:

` Cut-off drivers
` Drives 25 load
` Low power operation
` 2000V ESD protection
` Voltage compensated operating range = −4.2V to −5.7V
` Available to industrial grade temperature range


Pinout




Specifications

Storage Temperature (TSTG) ..................−65°C to +150°C
Maximum Junction Temperature (TJ) .......................+150°C
VEE Pin Potential to Ground Pin ..................−7.0V to +0.5V
Input Voltage (DC) VEE to......................................... +0.5V
Output Current (DC Output HIGH) .........................−100 mA
ESD (Note 2) ...........................................................2000V


Description

The 100354 contains eight D-type edge triggered, master/ slave flip-flops with individual inputs (Dn), true outputs (Qn), a clock input (CP), an output enable pin (OEN), and a common clock enable pin (CEN). Data enters the master when CP is LOW and transfers to the slave when CP goes HIGH. When the CEN input goes HIGH it overrides all other inputs, disables the clock, and the Q outputs maintain the last state.

A Q output of 100354 follows its D input when the OEN pin is LOW. A HIGH on OEN holds the outputs in a cut-off state. The cutoff state is designed to be more negative than a normal ECL LOW level. This allows the output emitter-followers to turn off when the termination supply is −2.0V, presenting a high impedance to the data bus. This high impedance reduces termination power and prevents loss of low state noise margin when several loads share the bus.

The 100354 outputs are designed to drive a doubly terminated 50 transmission line (25 load impedance). All inputs have 50 k pull-down resistors.